According to ST specs PNB should be 8 bit instead of 7
According to ST specs
It doesn't seem that in single bank mode two sector of 8 kb are teamed up in a single 16 kb sector. But I just confirmed this with a test! The information is not clear in the datasheets.
In any case, it seems that there is no difference in flash layout between STM32U5[78] chips and the rest of the chips. The only difference is the size of the memory. So I believe that the flash page size should be the same for the entire family
embassy-ci[bot]
commented
3 days ago
This addresses some of the issues listed here https://github.com/embassy-rs/embassy/issues/3561
According to ST specs PNB should be 8 bit instead of 7
According to ST specs
It doesn't seem that in single bank mode two sector of 8 kb are teamed up in a single 16 kb sector. But I just confirmed this with a test! The information is not clear in the datasheets.
In any case, it seems that there is no difference in flash layout between STM32U5[78] chips and the rest of the chips. The only difference is the size of the memory. So I believe that the flash page size should be the same for the entire family