davideschiavone
commented
4 months ago that is why we exclude it from being included automatically, (it also has functional bugs) anyway, if it is not included, after elaboration in synthesis that error does not affect anything - if you want, feel free to make a PR with the fix to have the analyze phase passing (please keep in comments the old "pow" functions)
DC synthesis reports some errors in the PDM2PCM IP:
Error: ../../../hw/vendor/esl_epfl_x_heep/hw/ip/pdm2pcm/rtl/halfband.sv:66: first argument of $pow should be or evaluate to a integer constant '2' or a real constant '2.0'. (ELAB-2083)https://github.com/esl-epfl/x-heep/blob/322f46674a234a7f012320c3747d6801dc8b65d5/hw/ip/pdm2pcm/rtl/halfband.sv#L66
Error: ../../../hw/vendor/esl_epfl_x_heep/hw/ip/pdm2pcm/rtl/fir.sv:51: first argument of $pow should be or evaluate to a integer constant '2' or a real constant '2.0'. (ELAB-2083)https://github.com/esl-epfl/x-heep/blob/322f46674a234a7f012320c3747d6801dc8b65d5/hw/ip/pdm2pcm/rtl/fir.sv#L51
According to the DC documentation, the function
$powof SystemVerilog only can have as first argument a 2 or 2.0 (at least in the 2023.12 version of the program). For example,$pow(2, power_value)or$pow(2.0, power_value).An easy way to solve these errors would be to change
$pow((TOTCOEFS-1)/2.0-k, 2)for((TOTCOEFS-1)/2.0-k)*((TOTCOEFS-1)/2.0-k)), but I don't know if they can be solved in any other way.