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esl-epfl / x-heep

eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
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Fix clk gating issue (patch) #584

Closed JoseCalero closed 2 months ago

JoseCalero commented 2 months ago

// In Zynq7000, just bypass the clock gating because there are not enough BUFGs that can be // cascaded with the BUFG of the MMCM. // In the Zynq UltraScale+, it can be implemented as BUFGCE without trouble, since there // are > 500 BUFGCEs and the rules for cascading are more relaxed. // NOTE: This cannot be substituted by a latch+and

JoseCalero commented 2 months ago

@LuigiGiuffrida98 @davideschiavone this should be OK :)

JoseCalero commented 2 months ago

@davideschiavone @LuigiGiuffrida98 this was verified in the FPGA, we can merge it

LuigiGiuffrida98 commented 2 months ago

Fine for me.