Verilog waccess not aligned with output data

[sinill57]

Problem:

When generating an AXI-lite interface, the internal output interface for a bitfield with hardware: oa option, the signal csr_*_out is one clock cycle behind csr_*_waccess.

This prevents from using waccess as a data_valid input for downstream modules.

Solution:

In the Verilog template corsair/templates/regmap_verilog.j2 we can change the combinatorial assignment assign {{ port_bf_waccess(reg, bf) }} = wready && {{ sig_csr_wen(reg) }}; to a registered one.

Is this behaviour a bug or done on purpose? If latter, what are the expected uses of this signal?

[esynr3z]

Well, as far as I remember this was done intentionally. Idea was to notify hardware as early as possible about ongoing read/write on the selected register. Then hardware can FF it if required or not. I can't remember, but for some design this non-registered hint was useful.

Anyway, registered version can be introduced, it is quite easy to implement as you found already.