EVM & Structure Standardisation by Reduction to Bit Compositor & BitWise Logic

[AhliLi]

The structure of the EVM and the data structures should be reduced to a minimum bitwise compositor and minimal logic tree, allowing for accurate accounting and implementations in all current and theorhetical environments. Though the initial structure requires extraction, parallelism and exhaustive host optimization WITHOUT constraints allows implementation of both the system and its accessory scripts in all host environments including quantum & photonic and electronic circuits. This constructor implementation will remain valid for any hardware (or software) implementation in or on any physical configuration.

[Arachnid]

...what?

[Ivshti]

markov chains?

[AhliLi]

For reference, here's some typical SOA implementations in linear, parallel, and non-linear from a few decades ago, in bitwise photonic implementations:

https://www.osapublishing.org/oe/fulltext.cfm?uri=oe-24-26-30245&id=356764 https://www.osapublishing.org/ol/abstract.cfm?uri=ol-23-16-1271

[AhliLi]

Explained further:

As in the above example, 100ghz through a standard photonic logic gate typical of the time when Al Gore invented the "Internet" has a bit-length of about 3 millimeters, the length of a Byte being 24mm across, and parallel operations of bitwise logic can be implemented easily in one photonic cycle.

Eliminating fixed-scope registers in EVM and reducing logic representation to well formed structure that exhaustively represents the process flow and its optimizations provides the maximal opportunity and efficiency in all implementations.

This optimal definition uses one cycle to load the constructor and composit the structures, then the host can select valid implementation for available hardware.

Parallel and higher efficiency cyclic processes are intrinsicly known and optimised with all fully formed process sequence elements included.

Appropriate machine logic is a simple primitive tree and includes various characteristics of the process flow.

Total number of required primitives is minimal and not influenced by "register" scope nor host implementation. Size in bits of the structure is less than fixed opcodes and provides full machine optimization especially for cyclic and parallel computations.

Using the optimal universal & standard logic and structure definitions, anyone can implement with certainty that the REAL process length is accurate and maximally efficient in implementation.

The underlying logic and structure definition and its representation is universally standard. (Code, logic, compilers, electronic circuits and other implementations, structured data, semantic graph, machine learning, AI solvers, ... all use the same convention.)

The efficiency gained in highly repetitive or parallel processes is overwhelming, the structure of the definition of both the data and the protocol is exhaustive and complete. ("Completeness": formally valid for all known cases.)

[Arachnid]

If you have a concrete proposal of some kind, feel free to write an EIP. I'm closing this issue because all you seem to be writing here is incomprehensible word salad.

[AhliLi]

No.