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eugene-tarassov / vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
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Question about porting to HBM memory #203

Closed Leo-Z-Li closed 5 months ago

Leo-Z-Li commented 5 months ago

Hi Mr. Eugene, i am trying to port this project to alveo u55c. One major change would be the memory because u55c only has HBM memory. I have a question regarding the C0_DDR4_AXI_CTRL signal as it appears to be used for ECC purposes. My question is why this signal needs to be connected to the qdma pcie, and can I simply remove this connection (marked yellow) because HBM does not have such an interface? any suggestions will be greatly appreciated:) image

eugene-tarassov commented 5 months ago

The signal allows access to memory controller registers from RISC-V or the host CPU. It can be used, for example, for diagnostics. It is not needed to run Linux. You can remove it.

Leo-Z-Li commented 5 months ago

Thank you for the clarify!

munozher commented 2 months ago

Hi Mr. Eugene, i am trying to port this project to alveo u55c. One major change would be the memory because u55c only has HBM memory. I have a question regarding the C0_DDR4_AXI_CTRL signal as it appears to be used for ECC purposes. My question is why this signal needs to be connected to the qdma pcie, and can I simply remove this connection (marked yellow) because HBM does not have such an interface? any suggestions will be greatly appreciated:) image

Hello, were you able to port the design to the U55C? I am interested in doing this as well. Thanks!

Leo-Z-Li commented 2 months ago

@munozher Hi, I do have a preliminary design but I haven't tested it on board yet because my board is broken and waiting for AMD to replace it. I can share the design with you for test if you are interested.

munozher commented 2 months ago

@Leo-Z-Li Hello, yes thanks! That would be very helpful and I could test it.

Leo-Z-Li commented 2 months ago

@munozher Great! You can reach me via email (leo.z.li@usc.edu) and I can give you the design files shortly.