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f4pga / f4pga-arch-defs

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
https://f4pga.org
ISC License
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Supporting Ultrascale+ is in plan? #2620

Open the-centry opened 2 years ago

the-centry commented 2 years ago

If there is a plan to support u+ device? Thanks so much!

mithro commented 2 years ago

See https://github.com/f4pga/prjuray - https://github.com/SymbiFlow/f4pga-arch-defs/pull/1651

GitHub
GitHub - f4pga/prjuray: Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format. - GitHub - f4pga/prjuray: Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bi...
mithro commented 2 years ago

Support for Ultrascale and Ultrascale+ will most likely end up happening through the FPGA Interchange Format rather than this architecture definitions approach.

You can see some initial xczu7ev support in that method -> https://chipsalliance.github.io/fpga-interchange-tests/#xczu7ev

FPGA interchange tests — fpga-interchange-tests 0.1 documentation
the-centry commented 2 years ago

Support for Ultrascale and Ultrascale+ will most likely end up happening through the FPGA Interchange Format rather than this architecture definitions approach.

You can see some initial xczu7ev support in that method -> https://chipsalliance.github.io/fpga-interchange-tests/#xczu7ev

FPGA interchange tests — fpga-interchange-tests 0.1 documentation

Ok,thanks so much! This project fpga-interchange seems like that next-pnr generate *bba through rapidwright,and the use next-pnr place and route! It may meet problem while device's data over the limit of capnp! It means that the work generating vpr's device data through rapidwright for Ultrascale+ is in plan?

FPGA interchange tests — fpga-interchange-tests 0.1 documentation