Define a process function which has included functions inside a where
clause.
Generate the VHDL code and try to simulate/synthesize the output.
The VHDL backend generates the output sub-functions in the VHDL code in the
same order as were defined in the design. This may result to using a
function in the VHDL code before defining it.
As a workaround, the designer could define the functions in the
define-then-use order which is not a common practice in functional programming.
Reported by shani...@gmail.com, Jan 19, 2010
To reproduce the problem:
The VHDL backend generates the output sub-functions in the VHDL code in the same order as were defined in the design. This may result to using a function in the VHDL code before defining it. As a workaround, the designer could define the functions in the define-then-use order which is not a common practice in functional programming.