Open HWoidt opened 8 years ago
Comment by HWoidt Thursday Jan 21, 2016 at 15:32 GMT
This issue is a bit more involved than initially thought:
There is a simulation mismatch between Haskell and VHDL concerning the Integer types:
For this specific example, the bug originates in the fact, that all processes are executed once initially. That way the nextState function is called once with the initial value of the delayOut signal, and not with the one assigned by the reset statement (if reset then delay = 0...).
This nextState function is not formally correct VHDL as it produces an invalid output for the valid (although not normally attainable) input of -128. This specific input value is the default initial value for the Integer type.
There are some options for solving this:
nextStateFun = $(newProcFun
[d| nextState state dir
= if dir == H then
if state < 9 then state + 1
else 0
else
if state <= 0 then 9
else state - 1
|])
I currently have no estimate of the amount of work needed for either 1. or 2.
Issue by ingo-sander Thursday Jan 14, 2016 at 14:42 GMT Originally opened as https://gits-15.sys.kth.se/ingo/forsyde-deep/issues/24
There seems to be a bug in the simulation with Modelsim.
When I simulate the counter example then Modelsim produces an error. I have not analyzed it further, but it might have to do with reset or the clock input. So, please ensure that a Modelsim simulation generates the trace for the clock signal and resets all flip-flops at the beginning of the simulation.
Here comes the code for the counter:
And here is the simulation output: