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fossi-foundation
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wishbone
Specification of the Wishbone SoC Interconnect Architecture
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Correction of a small typo in one of the headings
#25
mole99
opened
2 years ago
0
Is the Wishbone in itself licensed/protected in any way?
#24
m-kru
opened
2 years ago
13
Is the domain down?
#23
umarcor
opened
2 years ago
0
Operand size description within the specification is vague.
#22
m-kru
opened
3 years ago
2
DDR Protocol for physical buses
#21
jrmoserbaltimore
opened
4 years ago
1
uplevel subsection
#20
drom
opened
4 years ago
0
Rule 3.55: use ACK_O instead of ACK_I
#19
tgingold-cern
opened
4 years ago
0
License
#18
wallento
opened
5 years ago
0
added app note for wishbone use in a modern design
#17
ouabache
opened
5 years ago
0
Website
#16
wallento
closed
5 years ago
0
B3.1
#15
wallento
closed
5 years ago
0
Add build system README
#14
wallento
closed
5 years ago
0
Add cool diagrams from Verilog code!
#13
mithro
opened
5 years ago
1
Add information (link or import the info) about Etherbone
#12
mithro
opened
5 years ago
0
Add GitHub Actions workflow
#11
umarcor
opened
5 years ago
4
readme: fix url
#10
umarcor
closed
5 years ago
1
Merge recent review changes
#9
wallento
closed
5 years ago
1
Remaining issues in the spec
#8
tgingold-cern
closed
5 years ago
1
Editable version as Restructured text
#7
wallento
closed
5 years ago
0
b3 sources: drawing tool
#6
tgingold-cern
closed
5 years ago
1
b3 sources: should we keep appendix A (tutorial)
#5
tgingold-cern
closed
5 years ago
2
Complete 03_classic text
#4
tgingold-cern
closed
5 years ago
0
Complete 01_introduction.
#3
tgingold-cern
closed
5 years ago
1
Wishbone Public Domain Library for VHDL
#2
ams
opened
6 years ago
3
rst_i should not be a required signal
#1
olofk
opened
6 years ago
12