TODO

[ ] make PCells (see below)
[ ] add pyspice demos fir models and simulations
[ ] add notebooks with documentation
[ ] LVS. In LVS, the software will extract the fundamental components (e.g. diodes, transistors) based on the layout and compare it to the netlist
[ ] QRC extraction, or more accurately, RLCK parasitic elements. This is essential for RF circuits, otherwise, the simulation results are useless.
[ ] Customize main parametric components such as transistors, capacitors, diodes resistors, etc. Remember, those ready-made blocks you show in your video from Skywater are not very useful in this context as they are for automatic digital place and route. Once this is completed, a spice-compatible netlist is generated, and we can use ngspice and EEsim to display results etc.

Pcells to make

[x] NMOS
[ ] transistors
[ ] capacitors
[ ] diodes
[ ] resistors

Maybe

[ ] openroad plugin. Invoke Yosis from gdsfactory

@proppy @mithro @danchitnis @skandanc

daquintero commented 1 year ago

I'd be happy to help integrate a GDSFactory/OpenRoad plugin as I already have something similar I hope to be releasing soon!

joamatab commented 1 year ago

nice Dario,

we have also been thinking about integrating with vlsir

@growly @dan-fritchman

tcaduser commented 11 months ago

Is there any need for open source capacitance extraction?

daquintero commented 11 months ago

I've seen some really cool work in gplugins re Elmer capacitance extraction open source. I guess a demo on this Skywater 130nm pdk would be really cool for analogue/RF design!