geerlingguy
commented
3 months ago Reading through the Lichee Console 4A Wiki, there are a few important notes:
- The AliExpress listing shows the SoC running at 1.8 GHz, but the Wiki says "For the sake of Console battery life and heat generation, the current upper limit of the CPU frequency of the default image is limited to 1.5GHz." (under the 'Battery Life' section).
- The Wiki says "It can be powered by 12V DC 3.5mm interface or 5V USB-C port." — however many reviews mentioned they couldn't get USB-C charging to work.
- The GPU on the SoC is the "IMG™ B Series BXM-4-64" — I know there was some work towards making the open source driver available in Linux, not sure how far along that is.
Zepan
Basic information
Linux/system information
Benchmark results
CPU
Power
stress-ng --matrix 0): 9.3 Wtop500HPL benchmark: 8.5 WDisk
128 GB built-in eMMC
curl https://raw.githubusercontent.com/geerlingguy/pi-cluster/master/benchmarks/disk-benchmark.sh | sudo bashRun benchmark on any attached storage device (e.g. eMMC, microSD, NVMe, SATA) and add results under an additional heading. Download the script with
curl -o disk-benchmark.sh [URL_HERE]and runsudo DEVICE_UNDER_TEST=/dev/sda DEVICE_MOUNT_PATH=/mnt/sda1 ./disk-benchmark.sh(assuming the device issda).PiBenchmarks.com result (TODO_INSERT_LINK_HERE):
Network
iperf3results:Built-in Ethernet
iperf3 -c $SERVER_IP: 943 Mbpsiperf3 --reverse -c $SERVER_IP: 931 Mbpsiperf3 --bidir -c $SERVER_IP: 873 Mbps up, 199 Mbps downBuilt-in WiFi
iperf3 -c $SERVER_IP: 102 Mbpsiperf3 --reverse -c $SERVER_IP: 110 Mbpsiperf3 --bidir -c $SERVER_IP: 55 Mbps up, 27 Mbps down(Be sure to test all interfaces, noting any that are non-functional.)
GPU
GLMark2 ES2 Result:
The power consumption on the device jumped to 9.1W during the OpenGL tests. A tiny bit higher than the average CPU consumption during Geekbench tests.
Memory
tinymembenchresults:Click to expand memory benchmark result
``` tinymembench v0.4.10 (simple benchmark for memory throughput and latency) ========================================================================== == Memory bandwidth tests == == == == Note 1: 1MB = 1000000 bytes == == Note 2: Results for 'copy' tests show how many bytes can be == == copied per second (adding together read and writen == == bytes would have provided twice higher numbers) == == Note 3: 2-pass copy means that we are using a small temporary buffer == == to first fetch data into it, and only then write it to the == == destination (source -> L1 cache, L1 cache -> destination) == == Note 4: If sample standard deviation exceeds 0.1%, it is shown in == == brackets == ========================================================================== C copy backwards : 3141.5 MB/s C copy backwards (32 byte blocks) : 1359.6 MB/s (1.1%) C copy backwards (64 byte blocks) : 1339.0 MB/s (0.2%) C copy : 3214.8 MB/s C copy prefetched (32 bytes step) : 3227.4 MB/s C copy prefetched (64 bytes step) : 3229.1 MB/s C 2-pass copy : 2758.9 MB/s (0.1%) C 2-pass copy prefetched (32 bytes step) : 2712.3 MB/s C 2-pass copy prefetched (64 bytes step) : 2702.4 MB/s (0.2%) C fill : 11232.6 MB/s C fill (shuffle within 16 byte blocks) : 11228.5 MB/s (0.7%) C fill (shuffle within 32 byte blocks) : 1592.7 MB/s (0.2%) C fill (shuffle within 64 byte blocks) : 1592.2 MB/s --- standard memcpy : 3216.6 MB/s standard memset : 11227.0 MB/s ========================================================================== == Memory latency test == == == == Average time is measured for random memory accesses in the buffers == == of different sizes. The larger is the buffer, the more significant == == are relative contributions of TLB, L1/L2 cache misses and SDRAM == == accesses. For extremely large buffer sizes we are expecting to see == == page table walk with several requests to SDRAM for almost every == == memory access (though 64MiB is not nearly large enough to experience == == this effect to its fullest). == == == == Note 1: All the numbers are representing extra time, which needs to == == be added to L1 cache latency. The cycle timings for L1 cache == == latency can be usually found in the processor documentation. == == Note 2: Dual random read means that we are simultaneously performing == == two independent memory accesses at a time. In the case if == == the memory subsystem can't handle multiple outstanding == == requests, dual random read has the same timings as two == == single reads performed one after another. == ========================================================================== block size : single random read / dual random read 1024 : 0.0 ns / 0.0 ns 2048 : 0.0 ns / 0.0 ns 4096 : 0.0 ns / 0.0 ns 8192 : 0.0 ns / 0.0 ns 16384 : 0.0 ns / 0.0 ns 32768 : 0.0 ns / 0.0 ns 65536 : 0.1 ns / 0.1 ns 131072 : 17.3 ns / 26.3 ns 262144 : 26.1 ns / 34.1 ns 524288 : 32.4 ns / 39.0 ns 1048576 : 49.0 ns / 61.9 ns 2097152 : 97.0 ns / 131.3 ns 4194304 : 123.3 ns / 153.5 ns 8388608 : 147.7 ns / 181.1 ns 16777216 : 165.3 ns / 203.4 ns 33554432 : 180.7 ns / 227.0 ns 67108864 : 194.6 ns / 250.8 ns ```sbc-benchresultsRun sbc-bench and paste a link to the results here: https://sprunge.us/fUCnrY
Phoronix Test Suite
Results from pi-general-benchmark.sh: