The verilog model should only use language constructs supported by the tool chain, i.e. only compiler directives implemented in the synthesis tool yosys.
Actual Behavior
The current verilog module uses the compiler directive `suppress_faults that is not implemented in yosys.
In consequence, when loading the verilog model into yosys, i.e. via the openlane variable VERILOG_FILES_BLACKBOX,
yosys will stop with error:
Executing Verilog-2005 frontend:
/content/eda/share/pdk/gf180mcuC/libs.ref/gf180mcu_fd_io/verilog/gf180mcu_fd_io.v
/content/eda/share/pdk/gf180mcuC/libs.ref/gf180mcu_fd_io/verilog/gf180mcu_fd_io.v:17: ERROR: Unimplemented compiler directive or undefined macro `suppress_faults.
child process exited abnormally
Steps to Reproduce the Problem
within config.tcl,
set ::env(VERILOG_FILES_BLACKBOX) /content/eda/share/pdk/gf180mcuC/libs.ref/gf180mcu_fd_io/verilog/gf180mcu_fd_io.v
@proppy
Expected Behavior
The verilog model should only use language constructs supported by the tool chain, i.e. only compiler directives implemented in the synthesis tool yosys.
Actual Behavior
The current verilog module uses the compiler directive `suppress_faults that is not implemented in yosys. In consequence, when loading the verilog model into yosys, i.e. via the openlane variable
VERILOG_FILES_BLACKBOX, yosys will stop with error:Steps to Reproduce the Problem
Specifications