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globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
7 track standard cells for GF180MCU provided by GlobalFoundries.
https://gf180mcu-pdk.rtfd.io
Apache License 2.0
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Technology LEF files have incorrect CPERSQDIST
#30
RTimothyEdwards
opened
1 year ago
15
wrap unwrapped attributes of test_cell of `ff(IQ1,IQN1)` in quotations
#29
kareefardi
closed
1 year ago
5
liberty issues with yosys
#28
kareefardi
closed
1 year ago
0
Adding missing user defined primitives.
#27
mithro
closed
1 year ago
4
cells: rename functional module
#26
proppy
opened
1 year ago
10
.spice netlist is messed up due to label placement
#25
andylithia
opened
1 year ago
1
Gate level verilog modules are horribly broken and unusable
#24
RTimothyEdwards
opened
2 years ago
16
gf180mcu_fd_sc_mcu7t5v0_mux2_1 is seemingly not DRC clean
#23
gatecat
closed
1 year ago
8
Fixes buffer resizing for PnR tools
#22
QuantamHD
closed
2 years ago
6
tech: move SITE after UNITS
#21
proppy
closed
2 years ago
1
tech: add site definition
#20
proppy
closed
2 years ago
0
Missing Resistance for vias in tech lef
#19
kareefardi
opened
2 years ago
14
Missing SITE definition
#18
kareefardi
closed
2 years ago
3
Rename `METAL1` to `Metal1` in all cells `lef` to match the `techlef`
#17
kareefardi
closed
2 years ago
3
Miss-match in metal layer names between cells lef and tech lef
#16
kareefardi
closed
2 years ago
0
Fix liberty header names
#15
RTimothyEdwards
closed
2 years ago
0
Added missing liberty file headers.
#14
RTimothyEdwards
closed
2 years ago
1
Set up readthedocs pull request rendering
#13
mithro
opened
2 years ago
1
Figure out what is going on with the fill schematic rendering
#12
mithro
opened
2 years ago
0
Figure out how to fix the flip flop schematic rendering
#11
mithro
opened
2 years ago
0
Figure out how to fix the buffers schematic rendering
#10
mithro
opened
2 years ago
0
Fix broken standard cell schematic images
#9
mohanad0mohamed
closed
2 years ago
1
Fixing warnings
#8
mohanad0mohamed
closed
2 years ago
2
Updating prim names
#7
FaragElsayed2
closed
2 years ago
4
Adding definition.json files
#6
mohanad0mohamed
closed
2 years ago
3
Move documentation from base gf180mcu-pdk
#5
mithro
closed
2 years ago
1
Add verilog test benches for each of the standard cells.
#4
mithro
opened
2 years ago
0
Add missing definition.json files for each standard cell
#3
mithro
closed
2 years ago
0
CI should check that the standard cells pass the GF180MCU DRC rules
#2
mithro
opened
2 years ago
0
Get the foss-eda-tools.googlesource.com mirror happening
#1
mithro
closed
1 year ago
1