Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)
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Update example WORKSPACE contents in the README.md. #320
It would be useful to have a real complete WORKSPACE file, perhaps in a bazel_rules_hdl_example repo, tested nightly, that users could use as a starting point for their own RTL builds.
Small fix in sample WORKSPACE addition.
It would be useful to have a real complete WORKSPACE file, perhaps in a
bazel_rules_hdl_examplerepo, tested nightly, that users could use as a starting point for their own RTL builds.