Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)
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Give `extract_lef_and_liberty` an output group for just the default corner #337
It's reasonable for some consumers of extract_lef_and_liberty to only consume the default corner of the given PDK, so let's give them an option to skip all other corners.
It's reasonable for some consumers of
extract_lef_and_libertyto only consume the default corner of the given PDK, so let's give them an option to skip all other corners.