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hex-five / multizone-fpga

This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW platform for its MultiZone Trusted Execution Environment and MultiZone Trusted Firmware. The X300 is an enhanced secure version of the SiFive's Freedom E300 built around the Rocket chip developed at U.C. Berkeley.
http://hex-five.com
Apache License 2.0
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Add Hex Five JEDEC ID to riscv/riscv-openocd #6

Closed cgarlati closed 4 years ago

cgarlati commented 5 years ago

Request addition of Hex Five's JEDEC ID to https://github.com/riscv/riscv-openocd/blob/5d9f48640461fbac5c30958f63a01e666ee64dd4/src/helper/jep106.inc

cgarlati commented 5 years ago

@borancar Any progress?

borancar commented 5 years ago

We're in the June version, I'll trigger the OpenOCD flow now.

borancar commented 5 years ago

Patch sent to openocd mainline - http://openocd.zylin.com/#/c/5244/, waiting for merge before sending a PR to SiFive.