U250 support?

[YangZhou1997]

Hi authors,

Just wonder why U250 is not supported, given U200 and U280 are supported? are there any technical challenges when handling U250? If I want to port it to U250, would that be hard?

Best, Yang

[mariodruiz]

Hi,

We did not have an U250 neither the bandwidth to port the designs. The challenges is going to be to relocate the CMAC IP and memory controller banks.

Mario

[YangZhou1997]

Cool. Thanks, let me give it a try!

[YangZhou1997]

HI Mario,

I just ported the rep to U250 based on U200's configure. Now VIO shows everything normal. But when I tried the xdma driver and cmac_stats, /dev does not have xdma0_user or xdma0_xvc appearing, and thus cmac_stats cannot be executed.

Is it any misconfiure in the xdma IP core for U200, as I see in U200:

set xdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma_0 ]
  set_property -dict [ list \
   CONFIG.xdma_axi_intf_mm {AXI_Stream} \
 ] $xdma_0

While in U280:

set xdma_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xdma:4.1 xdma_0 ]
   set_property -dict [ list \
   CONFIG.PCIE_BOARD_INTERFACE {pci_express_x1} \
   CONFIG.PF0_DEVICE_ID_mqdma {9011} \
   CONFIG.PF2_DEVICE_ID_mqdma {9011} \
   CONFIG.PF3_DEVICE_ID_mqdma {9011} \
   CONFIG.axi_data_width {64_bit} \
   CONFIG.axilite_master_en {true} \
   CONFIG.axilite_master_size {8} \
   CONFIG.axisten_freq {250} \
   CONFIG.cfg_mgmt_if {false} \
   CONFIG.coreclk_freq {250} \
   CONFIG.en_gt_selection {true} \
   CONFIG.mode_selection {Advanced} \
   CONFIG.pcie_blk_locn {PCIE4C_X1Y0} \
   CONFIG.pf0_device_id {9011} \
   CONFIG.pf0_msi_enabled {false} \
   CONFIG.pf0_msix_cap_pba_bir {BAR_1} \
   CONFIG.pf0_msix_cap_table_bir {BAR_1} \
   CONFIG.pl_link_cap_max_link_speed {2.5_GT/s} \
   CONFIG.pl_link_cap_max_link_width {X1} \
   CONFIG.plltype {CPLL} \
   CONFIG.xdma_axi_intf_mm {AXI_Stream} \
   CONFIG.xlnx_ref_board {AU280} \
 ] $xdma_0

I do not have U280 in hand, and want to get you option -- should I modify U250 xdma setting according to U280 to make cmac_stats work?

Best, Yang

[mariodruiz]

The porting process is a bit more complex than that. You will need to open the IP integrator and configure the IP manually, there may be more than one IP to reconfigure.

Without going into the process I cannot be of assistance.

[YangZhou1997]

Yes, understand. But according to Xilinx spec about U200 and U250 (https://www.xilinx.com/support/documentation/data_sheets/ds962-u200-u250.pdf), they are almost the same except for LUT, BRAM number. They have the same pin constraint; I just changed the cmac group and core selection, and Limago works on U250 with the arpping, ping, and iperf2 applications

But one problem is that the iperf2 application is not consistently working -- after I run iperf2 once for 10second, the next run won't work. I need to rewrite the bitstream to make it work. The arpping and ping always work. Then I notice that the timing constraint is not met, see below

So I guess the unmet timing causes this behavior. Did you see this timing issue your platform? can U200 meet the constraints? It would be great if you can give some suggestions on fixing the timing constraint issue. I am new to FPGA, any specific suggestion to this issue, or tutorials, talks, slides are all good to me.

Best, Yang

[mariodruiz]

The timing is not that bad, you can try with a different implementation strategy. But the timing is not causing the issue. The issue you are seeing is a known bug that I am not able to look at the moment https://github.com/hpcn-uam/Limago/issues/7 I will make the same suggestion the ETH Zurich version is more active and does seems to have the issue.

Alveo U200 and U250 are not the same, they are different FPGAs, look at page 4 and 5 of this document https://www.xilinx.com/support/documentation/data_sheets/ds962-u200-u250.pdf