Is this only for PCIe connection or could be connected to AXI buses (on Zynq) directly?

[Pe3ucTop]

Hello, I'm trying implement this on Zynq Ultrascale with directly connecting to AXI buses. Do it need additional changes in design to accept such connection? Did you tried such implementation ? What changes need be done to driver ? Is it possible to decrease FPGA resource usage (at least 2 times) and which parameters affect it mostly?

[ctarver]

I just started investigating this project and am also interested in running it on non-PCI based FPGAs. @hsharma35, do you have any insight on this? How hard do you think it'd be to create the verilog, add it to a Vivado project, and then run the project with some sort of host code on the ARM of zynq?

[ctarver]

I was able to get started on version 1 of the project here: https://bitbucket.org/hsharma35/dnnweaver.public

It actually creates a vivado project for the network. I was able to synthesize for my FPGA. I'm currently trying to figure out the petalinux part to actually run the project.

[wxbbuaa2011]

@ctarver I also do this. But I encountered a problem when I simulated this project. The pu_controller_bin.vh file is generated by compiler. iverilog -o mydesign -c file.list will produce the error such as include/pu_controller_bin.vh:1: syntax error I give up. @hsharma35 Could you help me solve this problem? Thanks!

[mattpcaswell]

@ctarver I was able to get the design on my FPGA as well, but I was unable to get it functioning. Petalinux would completely crash every time I tried to communicate with the design. I'm a complete beginner at this and was unable to debug this issue in depth but it seemed like it was violating AXI protocols in some way. I hope you're able to take it further!

[wxbbuaa2011]

dnnweaver2.0 running environment how to build? This problem has been bothering me for a few weeks. Could you help me? Thanks very much.

[hsharma35]

@Pe3ucTop The Verilog for the project should be portable to any platform like the Zynq SoC or to other vendors like intel's FPGAs. The major change to support other platforms will be on the driver side (which should be provided by the vendors, or the software side.

[hsharma35]

I just started investigating this project and am also interested in running it on non-PCI based FPGAs. @hsharma35, do you have any insight on this? How hard do you think it'd be to create the verilog, add it to a Vivado project, and then run the project with some sort of host code on the ARM of zynq?

@ctarver I haven't tried this myself. We basically need the following interfaces:

1. The pci_cl_ctrl* AXI-Lite interface is used by CPU to write to registers in the FPGA.
2. The pci_cl_data* AXI4-Full interface is used to write from CPU to the BRAM in the FPGA.
3. The cl_ddr* AXI4-Full interface is used by dnnweaver accelerator on the FPGA fabric to write to/read from a shared DDR space.

You won't need to change any RTL for this. If the FPGA doesn't have enough resources, you can reduce the systolic array dimensions from the 32x32 default value to 16x16 or 8x8.

[ctarver]

Thanks for the feedback. I hope to be able to look into this eventually.

For the moment, I'm sticking with version 1 of the dnnweaver since it seems to be more ready to deploy on something like a zedboard. I'm trying to fill in the gaps in the instructions specifically regarding petalinux. I'll be reporting back my progress and steps that way the larger community can hopefully benefit from them.

[cbrl]

@ctarver Have you made any progress with DnnWeaver 1? I'm attempting to do the same with a Zynq-7000 board, but have run into some issues along the way. Particularly with initializing the accelerator program and loading the weights/biases and input data.

[ctarver]

@cbrl I haven't looked at this any further. We moved on to use the Xilinx DNNDK tools. I may circle back around to try DNNWeaver eventually.

[cbrl]

Okay, thanks. DNNDK looks pretty interesting.

[wxbbuaa2011]

Nice work