Closed Eriner closed 9 years ago
01:00.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc. [AMD/ATI] Tahiti XT [Radeon HD 7970/8970 OEM / R9 280X] [1002:6798] (prog-if 00 [VGA controller])
Subsystem: ASUSTeK Computer Inc. Tahiti XTL [Radeon R9 280X DirectCU II TOP] [1043:3006]
Flags: bus master, fast devsel, latency 0, IRQ 63
Memory at d0000000 (64-bit, prefetchable) [size=256M]
Memory at fea00000 (64-bit, non-prefetchable) [size=256K]
I/O ports at e000 [size=256]
Expansion ROM at fea40000 [disabled] [size=128K]
Capabilities: <access denied>
Kernel driver in use: radeon
Kernel modules: radeon
mesa built from iXit/mesa-3D master
Shader in question:
nine:pixelshader9:ctor: This=0x7c835c90 pParams=0x33ab68 pFunction=0x12f3b436 cso=(nil)
PS3.0
DEF c38 { -0.850000 0.017500 0.010000 1.000000 }
DEF c39 { 0.031250 0.015625 0.318310 0.166667 }
DEF c44 { 0.040000 -0.000000 -8.000000 1.000000 }
DEF c45 { 0.500000 6.283185 -3.141593 0.000000 }
DEF c50 { -1.000000 -2.000000 -3.000000 -9.000000 }
DEF c51 { -4.000000 -5.000000 -6.000000 -7.000000 }
DEF c56 { -2.000000 3.000000 -0.000000 -1.000000 }
DEF c57 { 0.000010 -16.609640 0.220000 0.030000 }
DEF c62 { 2.000000 -1.000000 0.000000 2.200000 }
DEF c63 { 0.002000 0.220000 0.300000 0.060000 }
DEF c68 { -0.033333 2.492837 0.454545 0.000000 }
DEFI iconst[0] { 5 0 0 0 }
DCL v0 TEXCOORD0
DCL v1.xyz_ TEXCOORD1
DCL v2.xyz_ TEXCOORD2
DCL v3.xyz_ TEXCOORD3
DCL v4 TEXCOORD4
DCL v5.xyz_ TEXCOORD5
DCL s0 2D
DCL s1 2D
DCL s2 2D
DCL s3 CUBE
DCL s4 2D
DCL s5 2D
DCL s6 2D
DCL s10 2D
DCL s11 2D
DCL s12 2D
DCL s13 2D
DCL s14 2D
TEX r0 v0 s2
ADD r0.xyz_ r0.wxyw c38
MAD r0._yz_ r0 c62.xxxx c62.yyyy
MUL r1.x___ -(r0).yyyy c209.wwww
DP2ADD r0._y__ r0.yzzw -(r0).yzzw c38.wwww
MAX r1._y__ r0.yyyy c62.zzzz
RSQ r0._y__ r1.yyyy
RCP r0._y__ r0.yyyy
DP3 r1._y__ v2 v2
RSQ r1._y__ r1.yyyy
DP3 r1.__z_ v3 v3
RSQ r1.__z_ r1.zzzz
MUL r2.xyz_ r1.zzzz v3.zxyw
MUL r2.xyz_ r0.zzzz r2
MUL r1._yzw r1.yyyy v2.xzxy
MAD r1.xyz_ r1.xxxx r1.yzww r2
DP3 r0.__z_ v1 v1
RSQ r0.__z_ r0.zzzz
MUL r2.xyz_ r0.zzzz v1.zxyw
MAD r1.xyz_ r0.yyyy r2 r1
DP3 r0._y__ r1 r1
RSQ r0._y__ r0.yyyy
MUL r1.xyz_ r0.yyyy r1
LOG r2.x___ c204.xxxx
LOG r2._y__ c204.yyyy
LOG r2.__z_ c204.zzzz
MUL r2.xyz_ r2 c62.wwww
EXP r3.x___ r2.xxxx
EXP r3._y__ r2.yyyy
EXP r3.__z_ r2.zzzz
MOV r2.x___ c37.xxxx
CMP r0._y__ r0.xxxx r2.xxxx c26.xxxx
MAD r2.__z_ r0.yyyy c39.xxxx c39.yyyy
RCP r0._y__ v4.wwww
MOV r1.___w c38.wwww
MUL r4 r1.yyyy c111
MAD r4 c110 r1.xxxx r4
MAD r4 c112 r1.zzzz r4
ADD r4 r4 c113
DP4 r4.__z_ r1 r4
MUL r5 r1.yyyy c103
MAD r5 c102 r1.xxxx r5
MAD r5 c104 r1.zzzz r5
ADD r5 r5 c105
DP4 r4.x___ r1 r5
MUL r5 r1.yyyy c107
MAD r5 c106 r1.xxxx r5
MAD r5 c108 r1.zzzz r5
ADD r5 r5 c109
DP4 r4._y__ r1 r5
MOV r0.__z_ c39.zzzz
MUL r0.__z_ r0.zzzz c214.xxxx
MOV r2.___w c38.wwww
MUL r5.xyz_ r4 r0.zzzz
TEXLDD r6 r2.wzzw s13 c62.zzzz c62.zzzz
It seems the code is correct, but not the assert. Changing src[3] to src[1] in the assert (nine_shader.c line 2609) should solve it
Changing code and will report back after re-compile. Thanks
you need to replace the two src[3] of the assert
ah, I thought I did; I'm an idiot.
welp.
nine_shader.c:2626:NineTranslateInstruction_TEXLDL: Assertion
tx->insn.src[3].idx >= 0 && tx->insn.src[3].idx < (sizeof(tx->sampler_targets)/sizeof((tx->sampler_targets)[0]))' failed.`
Need another debug log?
same problem src[3] src[1]
will s/src[3]/src[1] and do the same for subsequent issues if/when they occur.
that seems to have fixed the issue, thanks @axeldavy, you're the man! You may close this when the issue is officially resolved/at your discretion.
Fix pushed
Confirming that this has fixed the issue, thanks.
Debug log: http://pastebin.com/raw.php?i=uTVEtA0X
nine_shader.c:2610:NineTranslateInstruction_TEXLDD: Assertion``tx->insn.src[3].idx >= 0 && tx->insn.src[3].idx < (sizeof(tx->sampler_targets)/sizeof((tx->sampler_targets)[0]))' failed.
wine: Unhandled exception 0x80000003 in thread 42 at address 0xf65e9fd3 (thread 0042), starting debugger...