Closed arblake closed 3 years ago
No responses
I'm sorry that I couldn't help you.
On Mon, 12 Oct 2020, 15:06 Adrian Blake, notifications@github.com wrote:
No responses
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Rob,
It is not a problem with your software ... but a hardware or boot problem.
You have been very helpful.
Adrian
Rob, Could it be with the "tinyfpga_bx_usbserial" and how it interact with hardware?
It could be, I'm a novice at this, but that worked on the hacker. Maybe valentyusb could be used?
On Mon, 12 Oct 2020, 16:00 Adrian Blake, notifications@github.com wrote:
Rob, Could it be with the "tinyfpga_bx_usbserial" and how it interact with hardware?
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I'm not familiar with j1eforth, but if it's using tinyfpga_bx, does it pass timing? I know the original tinyfpga USB stuff would synthesize, but wouldn't meet timing by a longshot. When an FPGA doesn't meet timing, you get weird behaviour like you're seeing.
What is the architecture of j1eforth? Does it use valentyusb?
Looking at the output in https://github.com/rob-ng15/Silice-Playground/tree/master/j1eforth/FOMU#resources-on-the-fomu the issue appears to be that it meets timing at 25 MHz, but USB is running at 48 MHz, so you're overclocking the system by almost 2x. FPGAs tend to be conservatively binned, so it will work on some FPGAs but not others.
Also make sure that you are the right pins. The Hacker and PVT board use different pins.
Would it be advisable to try valentyusb? I only used the tiny USB stack as I discovered it on here. I am a novice at FPGA programming.
On Mon, 12 Oct 2020, 17:30 Tim Ansell, notifications@github.com wrote:
Also make sure that you are the right pins. The Hacker and PVT board use different pins.
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Either ValentyUSB or LUNA would be good options. The #nmigen channel on irc.freenode.net is very helpful around questions for that.
I opened up an issue at https://github.com/rob-ng15/Silice-Playground/issues/8 because it looks like more people are running into this issue.
j1eforth built with Silice works on a hacker board but not on PVT board. Any suggestions?