Open andreiw opened 11 months ago
According to the ISA doc, "Instruction-address-misaligned exceptions are not possible on machines that support extensions with 16-bit aligned instructions, such as the compressed instruction-set extension, C.". See page 21 of 20191213.
In short, it's easy to add EXCEPT_RISCV_INST_MISALIGNED handling, but impossible to test it, short of hacking together a custom qemu/sbi/edk2 build to target rv64g instead of rv64gc. Will skip this, esp. given the corner case (not running with an MMU, which is an unsupported scenario anyway).
I've never seen this in the wild, but I suppose it is possible.