Gray Binary Converter

[quekyj]

Description & Motivation

Add converter for binary-to-gray and gray-to-binary.

Related Issue(s)

50

Testing

Test is compared with manually hand calculated data.

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

No

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

Yes.

[quekyj]

@mkorbel1 any idea why this test fail?

00:09 +120 -1: test\configurator_test.dart: fifo configurator should generate FIFO [E]
  Expected: contains '(wrPointer == 3\'h6'
    Actual: '/**\n'
              ' * Generated by ROHD - www.github.com/intel/rohd\n'
              ' * Generation time: 2024-01-12 10:14:52.310 +08:00\n'
              ' * ROHD Version: 0.5.0\n'
              ' */\n'
              '\n'
              'module RegisterFile(\n'
              'input logic [5:0] wr_data_0,\n'
              'input logic [2:0] rd_addr_0,\n'
              'input logic [2:0] wr_addr_0,\n'
              'input logic clk,\n'
              'input logic reset,\n'
              'input logic wr_en_0,\n'
              'input logic rd_en_0,\n'
              'output logic [5:0] rd_data_0\n'
              ');\n'
              'logic [5:0] storageBank_0;\n'
              'logic [5:0] storageBank_1;\n'
              'logic [5:0] storageBank_4;\n'
              'logic [5:0] storageBank_3;\n'
              'logic [5:0] storageBank_2;\n'
              'logic [5:0] storageBank_5;\n'
              'logic [5:0] storageBank_6;\n'
              '//  combinational\n'
              'always_comb begin\n'
              '  if((~rd_en_0)) begin\n'
              '      rd_data_0 = 6\'h0;\n'
              '  end   else begin\n'
              '      case (rd_addr_0) \n'
              '          3\'h0 : begin\n'
              '              rd_data_0 = storageBank_0;\n'
              '          end\n'
              '          3\'h1 : begin\n'
              '              rd_data_0 = storageBank_1;\n'
              '          end\n'
              '          3\'h2 : begin\n'
              '              rd_data_0 = storageBank_2;\n'
              '          end\n'
              '          3\'h3 : begin\n'
              '              rd_data_0 = storageBank_3;\n'
              '          end\n'
              '          3\'h4 : begin\n'
              '              rd_data_0 = storageBank_4;\n'
              '          end\n'
              '          3\'h5 : begin\n'
              '              rd_data_0 = storageBank_5;\n'
              '          end\n'
              '          3\'h6 : begin\n'
              '              rd_data_0 = storageBank_6;\n'
              '          end\n'
              '          default : begin\n'
              '              rd_data_0 = 6\'h0;\n'
              '          end\n'
              '      endcase\n'
              '\n'
              '  end \n'
              '\n'
              'end\n'
              '\n'
              '//  sequential\n'
              'always_ff @(posedge clk) begin\n'
              '  if(reset) begin\n'
              '      storageBank_0 <= 6\'h0;\n'
              '      storageBank_1 <= 6\'h0;\n'
              '      storageBank_2 <= 6\'h0;\n'
              '      storageBank_3 <= 6\'h0;\n'
              '      storageBank_4 <= 6\'h0;\n'
              '      storageBank_5 <= 6\'h0;\n'
              '      storageBank_6 <= 6\'h0;\n'
              '  end   else begin\n'
              '      if((wr_en_0 & (wr_addr_0 == 3\'h0))) begin\n'
              '          storageBank_0 <= wr_data_0;\n'
              '      end \n'
              '\n'
              '      if((wr_en_0 & (wr_addr_0 == 3\'h1))) begin\n'
              '          storageBank_1 <= wr_data_0;\n'
              '      end \n'
              '\n'
              '      if((wr_en_0 & (wr_addr_0 == 3\'h2))) begin\n'
              '          storageBank_2 <= wr_data_0;\n'
              '      end \n'
              '\n'
              '      if((wr_en_0 & (wr_addr_0 == 3\'h3))) begin\n'
              '          storageBank_3 <= wr_data_0;\n'
              '      end \n'
              '\n'
              '      if((wr_en_0 & (wr_addr_0 == 3\'h4))) begin\n'
              '          storageBank_4 <= wr_data_0;\n'
              '      end \n'
              '\n'
              '      if((wr_en_0 & (wr_addr_0 == 3\'h5))) begin\n'
              '          storageBank_5 <= wr_data_0;\n'
              '      end \n'
              '\n'
              '      if((wr_en_0 & (wr_addr_0 == 3\'h6))) begin\n'
              '          storageBank_6 <= wr_data_0;\n'
              '      end \n'
              '\n'
              '  end \n'
              '\n'
              'end\n'
              '\n'
              'endmodule : RegisterFile\n'
              '\n'
              '////////////////////\n'
              '\n'
              'module Fifo(\n'
              'input logic readEnable,\n'
              'input logic [5:0] writeData,\n'
              'input logic reset,\n'
              'input logic clk,\n'
              'input logic writeEnable,\n'
              'output logic [5:0] readData,\n'
              'output logic error,\n'
              'output logic empty,\n'
              'output logic [2:0] occupancy,\n'
              'output logic full\n'
              ');\n'
              'logic [2:0] rd_addr_0;\n'
              'logic [2:0] wr_addr_0;\n'
              'logic wr_en_0;\n'
              'logic rd_en_0;\n'
              'logic [5:0] data;\n'
              'logic peekWriteData;\n'
              'logic matchedPointers;\n'
              'logic bypass;\n'
              'assign rd_en_0 = 1\'h1;\n'
              'assign readData = peekWriteData ? writeData : data;  // mux\n'
              'RegisterFile  rf(.wr_data_0(writeData),.rd_addr_0(rd_addr_0),.wr_addr_0(wr_addr_0),.clk(clk),.reset(reset),.wr_en_0(wr_en_0),.rd_en_0(rd_en_0),.rd_data_0(data));\n'
              'assign matchedPointers = wr_addr_0 == rd_addr_0;  // equals\n'
              'assign empty = matchedPointers & (~full);  // and_\n'
              '//  sequential\n'
              'always_ff @(posedge clk) begin\n'
              '  if(reset) begin\n'
              '      wr_addr_0 <= 3\'h0;\n'
              '      rd_addr_0 <= 3\'h0;\n'
              '      full <= 1\'h0;\n'
              '  end   else begin\n'
              '      if((~bypass)) begin\n'
              '          wr_addr_0 <= (writeEnable ? ((wr_addr_0 == 3\'h6) ? 3\'h0 : (wr_addr_0 + 3\'h1)) : wr_addr_0);\n'
              '          rd_addr_0 <= (readEnable ? ((rd_addr_0 == 3\'h6) ? 3\'h0 : (rd_addr_0 + 3\'h1)) : rd_addr_0);\n'
              '      end \n'
              '\n'
              '      full <= ((full & (writeEnable == readEnable)) | (((rd_addr_0 == ((wr_addr_0 == 3\'h6) ? 3\'h0 : (wr_addr_0 + 3\'h1))) & writeEnable) & 
(~readEnable)));\n'
              '  end \n'
              '\n'
              'end\n'
              '\n'
              'assign wr_en_0 = writeEnable & (~bypass);  // and__3\n'
              'assign bypass = (empty & readEnable) & writeEnable;  // and__4\n'
              'assign peekWriteData = empty & writeEnable;  // and__6\n'
              'assign error = ((empty & readEnable) & (~writeEnable)) | ((full & writeEnable) & (~readEnable));  // or__0\n'
              '//  sequential_0\n'
              'always_ff @(posedge clk) begin\n'
              '  if(reset) begin\n'
              '      occupancy <= 3\'h0;\n'
              '  end   else begin\n'
              '      unique case (({writeEnable,readEnable})) \n'
              '          2\'h2 : begin\n'
              '              occupancy <= (occupancy + 3\'h1);\n'
              '          end\n'
              '          2\'h1 : begin\n'
              '              occupancy <= (occupancy - 3\'h1);\n'
              '          end\n'
              '          default : begin\n'
              '              occupancy <= occupancy;\n'
              '          end\n'
              '      endcase\n'
              '\n'
              '  end \n'
              '\n'
              'end\n'
              '\n'
              'endmodule : Fifo'
     Which: does not contain '(wrPointer == 3\'h6'

  package:matcher                    expect
  test\configurator_test.dart 168:7  main.<fn>.<fn>

[mkorbel1]

@quekyj I dont see the test failing when I check out your branch locally? Try pulling main in and rerun?