Fix memory model handling of different edge and latency situations - Githubissues

intel / rohd-hcl

A hardware component library developed with ROHD.

https://pub.dev/packages/rohd_hcl

BSD 3-Clause "New" or "Revised" License

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Fix memory model handling of different edge and latency situations #71

Closed mkorbel1 closed 10 months ago

mkorbel1 commented 10 months ago

Description & Motivation

This PR:

Fix bugs related to memory model sampling on negative edges and improper handling of zero-latency accesses.
Fix error handling and assertions in constructing Memory (e.g. bug where assertion fired incorrectly)
Updates doc/README with more components
Update APB tracker to have configurable widths for addr and data

Related Issue(s)

N/A

Testing

Added new tests

Backwards-compatibility

Is this a breaking change that will not be backwards-compatible? If yes, how so?

No

Documentation

Does the change require any updates to documentation? If so, where? Are they included?

No