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ipbus
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ipbus-firmware
Firmware that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol
https://ipbus.web.cern.ch
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Switch to vivado 2018.3 in ci job configuration
#92
alessandrothea
closed
5 years ago
2
IPbus support in UVVM
#91
m-kru
closed
5 years ago
0
Task/89 - Simplify board-specific simulation top-levels
#90
alessandrothea
closed
5 years ago
3
Simplify board-specific simulation top-levels
#89
alessandrothea
closed
5 years ago
0
Removing outdated simulation setup files. Task/87
#88
alessandrothea
closed
5 years ago
3
Remove outdated lib_mapping.tcl setup file
#87
alessandrothea
closed
5 years ago
0
Add ZCU102 basex example design
#86
tswilliams
closed
5 years ago
1
Slave ipbus_ctrs_ported : Add missing 'READ_ONLY' generic
#85
tswilliams
closed
5 years ago
1
ipbus_peephole_ram, is it still a thing?
#84
alessandrothea
closed
5 years ago
6
Adding ram test benches and 72bit wide dual-port rams
#83
alessandrothea
closed
5 years ago
3
Adding 72bit-wide dual-port ipbus slaves
#82
alessandrothea
closed
5 years ago
0
Add test coverage for ipbus ram slaves
#81
alessandrothea
closed
5 years ago
1
ipbus_clk_bridge.vhd is broken
#80
blazra
opened
6 years ago
2
Bug/77
#79
dmnewbold
closed
6 years ago
1
adding components/amba_axi_lite/
#78
ruck314
closed
6 years ago
3
Bug in simulation clock block
#77
dmnewbold
closed
6 years ago
0
example design for zcu102 - basex
#76
kristianharder
closed
5 years ago
1
Update sim infra to have output clock of configurable frequency
#75
tswilliams
closed
6 years ago
1
Add first version of gitlab CI config
#74
tswilliams
closed
6 years ago
1
Use gitlab CI for automated builds & tests
#73
tswilliams
closed
5 years ago
1
Adding aux clock outputs to sim infra
#72
dmnewbold
closed
6 years ago
1
Enhancement/68
#71
dmnewbold
opened
6 years ago
0
Enhancement/68
#70
dmnewbold
closed
6 years ago
0
Enhancement/67 - Adding frequency counter block to ipbus
#69
dmnewbold
closed
5 years ago
1
Adding ATFC board example design to ipbus repo
#68
dmnewbold
opened
6 years ago
1
Adding frequency counter block to ipbus
#67
dmnewbold
closed
5 years ago
1
KCU105 - PHY SGMII
#66
kadamidi
opened
6 years ago
0
Adding read / write functionality to counter block
#65
dmnewbold
closed
6 years ago
2
Counter block needs to be (optionally) writeable
#64
dmnewbold
closed
5 years ago
3
KCU105 example design : Remove unused clock from constraints
#63
tswilliams
closed
6 years ago
0
Remove unused clock from KCU105 example design's clock constraints
#62
tswilliams
closed
6 years ago
1
bug/59: fix to dpram design
#61
dmnewbold
closed
6 years ago
0
Enhancement/57
#60
dmnewbold
closed
5 years ago
1
error message for ipbus_dpram in VIVADO 2017.4
#59
mkrivda
closed
6 years ago
4
ipbus UDP core causes DRC check failure on ultrascale+
#58
dmnewbold
opened
6 years ago
1
Adding aux clock functionality to kcu105 design
#57
dmnewbold
closed
5 years ago
1
VC707 IPbus - Working for some time and then it stops
#56
ixiotidi
closed
4 years ago
11
Additional CI jobs to run syntax checks and sim pings on every job
#55
alessandrothea
closed
6 years ago
1
ip/mac addresses converted to generics. See #51
#54
alessandrothea
closed
6 years ago
1
CI: Include syntax checks and simulation ping in test scripts
#53
alessandrothea
closed
5 years ago
0
KCU105 example communication problem
#52
kadamidis
closed
6 years ago
6
Turn sim's IP and MAC address into generics
#51
alessandrothea
closed
5 years ago
1
Broken dependency files
#50
alessandrothea
closed
4 years ago
1
Remove outdated slaves.vhd file
#49
alessandrothea
closed
6 years ago
0
Bug/43
#48
dmnewbold
closed
6 years ago
0
bug/41: updating ASYNC_REG constraints in ipbus_syncreg
#47
dmnewbold
closed
6 years ago
0
Adding SGMII ethernet for 7 series
#46
dmnewbold
opened
6 years ago
0
IPbus for VC707 - SGMII PHY
#45
ixiotidi
closed
6 years ago
17
Updated pinout constrains to detect 'cfg' ports automatically. See #42
#44
alessandrothea
closed
6 years ago
0
Fixes to ipbus_example design
#43
dmnewbold
closed
6 years ago
0
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