Open j0ono0 opened 3 years ago
Lattice has an application note: Using Differential I/O that has just a dotted line around the pairs:
Perhaps something similar to "group" the pinout labels?
Depends a bit if they are always diff pairs or not to begin with. In a FPGA it's often configurable whether they act as a diff pair or not.
But in general just having a + / - signs on the respective pins and a common prefix for the name is enough, don't really need anything fancy. It gets more complicated when the pins are not next to each other :/ And yeah, that happens ...
@j0ono0
Few ideas borrowed from various places:
IMO that Lattice(TM) diagram with dotted/dashed lines is counter-intuitive (my mind thinks to some parasitic shielding).
Thanks for the fast responses and comments everyone! some notes of my own (largely in response and extending other comments)...
Label text as an indicator for differential pair pins - Label content is 100% user supplied so this can be catered for as users preprocess content. Python is also well suited to list manipulation via list-comprehensions -- so my feeling is to leave this up to users rather than build in some enforced standard.
I've given some thought to a method of graphically linking pin locations:
...technically it would only require a new leader-line but might through up some complexities around how user would document x2 pins for labels.
On further reflection I wondered if compactness is not such a good goal - especially for complex hardware that is likely to have printed/PDF docs in A4 (or Letter) format. On that thought I mocked up what a full pinout graphic might be:
By pulling out each set of pins it:
On capability to achieve such a layout with pinout, I think it might already technically possible, but need try/review/amend before claiming that victory.
So, after a day of pondering it, I feel the latter example might be a better goal to aim for? Open to other opinions and input to my thinking.
A plus por minus sign after the name is simple and clear enough IMO
A bit more browsing online and I'm seeing and (slowly) understanding a bit better. Pin naming conventions quite clearly document the association once one is aware of them.
Keeping an open mind as I've spied some twitter opinion to come it still.
@j0ono0
I personally like idea A
(elegant and compact label) with some amends:
Another rule: In 99% of cases diff pair pins will be in the same places (as pair) otherwise it fails the impedance constrains on the very PCB, so YES this compactization (idea A) of label pairs can be on the account. Probably some slow diff signals like RS485 may afford pins that are not at the same place but those are labeled as A and B by whole industry (not even highlighting their differential nature in many cases).
@j0ono0
I personally like
idea A
(elegant and compact label) with some amends:
- add +/- extra symbol or _P _N to label
- longer arrow line to touch booth physical pins/holes (now touches one)
- add | symbol in between physical pins/holes (just like it is between the labels)
Another opinion (last): Variant C or even better B (of arrow) in your second graph/draw solves my last two amends in most elegant way.
I also like the idea of _P and _N naming.
Feedback seems to suggest naming conventions are adequate to communicate the diferential-pair relation. I still haven't ruled out creating some graphical icon down the track. Some twitter posts combined with a recent layout experiment matched up nicely so I thought it worth recording here --
'double-layer' sample generated with pinout (thanks to @somhi for suggesting it):
Mockup of possible 'joining' icon:
I'm attempting to find and ideal way to document differential pair pins with pinout.
If you have experience with them and opinions on how you would like to see them documented in a pinout diagram feel free to post and comment on the discussion here :)
Edit: added image with sample labeling as seen on twitter