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jameshegarty / rigel

Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.
MIT License
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Why doesn't everything get a reset fn? #106

Open jameshegarty opened 6 years ago

jameshegarty commented 6 years ago

It seems like we only have a reset fn if stateful==true, but why? Almost all modules will require a reset due to pipelining registers? Why not just include reset for everything?

& then get rid of stateful annotation b/c this is not used for anything else?

actually, pipeline registers aren't even being reset currently!!

jameshegarty commented 6 years ago

Perhaps systolic should just automagically build a reset for everything

jameshegarty commented 6 years ago

Correction: systolic doesn't generate pipeline valid bits (only pipeline registers, which don't need to be reset). Valids are calculated based on the static delay. So, systolic modules only require a reset if they have explicit state.