Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.
Coverage decreased (-38.3%) to 35.134% when pulling 20134a7b99547fca1f024baeee18d53b9eaefcf2 on moreBRAMoptions into dab3210312a23ab321625bad3b9f521631b7762e on master.
Coverage decreased (-38.3%) to 35.134% when pulling 20134a7b99547fca1f024baeee18d53b9eaefcf2 on moreBRAMoptions into dab3210312a23ab321625bad3b9f521631b7762e on master.