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jameshegarty / rigel

Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FPGAs, and also can compile to fast x86 test code using Terra.
MIT License
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terra :calculateHandshake() not created if input/output type aren't handshake #86

Open jameshegarty opened 6 years ago

jameshegarty commented 6 years ago

With handshake sources/sinks, we now need to create a :calculateHandshake() even if the module input/output type aren't handshake (the Handshake stuff may be fully internal to the module)

jameshegarty commented 6 years ago

Actually, if we disallow null->HS(A) types, this shouldn't happen. (we may need to look and see if this communicates with any globals that are HS.