Variable intialization at declare time

[MrDaiki]

Issue

This is a duplicate of issue #899 based on #901 refactoring of pre-typing. The feature requested is to add a new syntax that authorize variable initialization when they are declared.

The syntax is as follow :

reg u64 x=1,y=2,z,t=3;

Implementation

With the proposed implementation, we can also initialize multiple variables at the same time:

reg u64 x=1,y=2,z,t=3;

The current implementation doesn't support array initializing with this feature because array can currently be explicitly created only at top level. Allowing it would require reworking a large part of the grammar and pre-typing analysis.

In terms of semantic, the proposed implementation works as follow :

reg u64 x=3;

is abstractly equivalent to :

reg u64 x;
x=3;

[vbgl]

I did some cleaning and spotted a bug (see the fresh test case): checking of the LHS should occur before the RHS is added to the environment.

[MrDaiki]

I did some cleaning and spotted a bug (see the fresh test case): checking of the LHS should occur before the RHS is added to the environment.

To solve this case, I think we will need to call tt_expr instead of tt_assign (or we consider that tt_assign checks can be redundant)

[vbgl]

I’ve done the small changes you suggested. I let Alexandre decide whether he wants to change the data-type.