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jeanthom / gram

DDR3 controller for nMigen (WIP)
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ECP5 PHY signal lignes are invalid #18

Closed jeanthom closed 4 years ago

jeanthom commented 4 years ago

For the "A" lines this is related to invalid data in "dfi.phases[0].address[i]"

jeanthom commented 4 years ago

Related issue: https://github.com/nmigen/nmigen/issues/418

jeanthom commented 4 years ago

Workaround in https://github.com/jeanthom/gram/commit/7b509938d7fbffb96de8223f3e676d75a70d0d5f