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jeanthom / gram

DDR3 controller for nMigen (WIP)
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DRAM is not responding to read requests #29

Closed jeanthom closed 4 years ago

jeanthom commented 4 years ago

Chronogram of the DRAM signals

jeanthom commented 4 years ago

Full simulation (beware huge file when uncompressed): simsoc.07072020.zip

jeanthom commented 4 years ago

The issue seems to be related to a missing clk_n signal (fixed in https://github.com/jeanthom/gram/commit/c763fc2458b11453b26d802335a31abbc491ed7a). We currently get reports from the DDR model for other issues.