Fix bank activation failure

jeanthom commented 4 years ago
From simulation output: simsoc.09072020.zip
simsoctb.ram_chip.reset at time 0.0 ps WARNING:         200 (actually 200) us is required before RST_N goes inactive.
simsoctb.ram_chip.cmd_task: at time 4167762500.0 ps INFO: Precharge Power Down Enter
simsoctb.ram_chip.cmd_task: at time 5535762500.0 ps ERROR: tPD maximum violation during Power Down Exit
simsoctb.ram_chip.cmd_task: at time 5535762500.0 ps INFO: Power Down Exit
simsoctb.ram_chip.cmd_task: at time 9507792500.0 ps INFO: Load Mode 2
simsoctb.ram_chip.cmd_task: at time 9507792500.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7
simsoctb.ram_chip.cmd_task: at time 9507792500.0 ps INFO: Load Mode 2 CAS Write Latency =           5
simsoctb.ram_chip.cmd_task: at time 9507792500.0 ps INFO: Load Mode 2 Auto Self Refresh = Disabled
simsoctb.ram_chip.cmd_task: at time 9507792500.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal
simsoctb.ram_chip.cmd_task: at time 9507792500.0 ps INFO: Load Mode 2 Dynamic ODT Rtt =          60 Ohm
simsoctb.ram_chip.cmd_task: at time 12979792500.0 ps INFO: Load Mode 3
simsoctb.ram_chip.cmd_task: at time 12979792500.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern
simsoctb.ram_chip.cmd_task: at time 12979792500.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled
simsoctb.ram_chip.cmd_task: at time 16451792500.0 ps INFO: Load Mode 1
simsoctb.ram_chip.cmd_task: at time 16451792500.0 ps INFO: Load Mode 1 DLL Enable = Enabled
simsoctb.ram_chip.cmd_task: at time 16451792500.0 ps INFO: Load Mode 1 Output Drive Strength =          34 Ohm
simsoctb.ram_chip.cmd_task: at time 16451792500.0 ps INFO: Load Mode 1 ODT Rtt =          60 Ohm
simsoctb.ram_chip.cmd_task: at time 16451792500.0 ps INFO: Load Mode 1 Additive Latency = 0
simsoctb.ram_chip.cmd_task: at time 16451792500.0 ps INFO: Load Mode 1 Write Levelization = Disabled
simsoctb.ram_chip.cmd_task: at time 16451792500.0 ps INFO: Load Mode 1 TDQS Enable = Disabled
simsoctb.ram_chip.cmd_task: at time 16451792500.0 ps INFO: Load Mode 1 Qoff = Enabled
simsoctb.ram_chip.cmd_task: at time 19923792500.0 ps INFO: Load Mode 0
simsoctb.ram_chip.cmd_task: at time 19923792500.0 ps INFO: Load Mode 0 Burst Length =  8
simsoctb.ram_chip.cmd_task: at time 19923792500.0 ps INFO: Load Mode 0 Burst Order = Sequential
simsoctb.ram_chip.cmd_task: at time 19923792500.0 ps INFO: Load Mode 0 CAS Latency =           6
simsoctb.ram_chip.cmd_task: at time 19923792500.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL
simsoctb.ram_chip.cmd_task: at time 19923792500.0 ps INFO: Load Mode 0 Write Recovery =           5
simsoctb.ram_chip.cmd_task: at time 19923792500.0 ps INFO: Load Mode 0 Power Down Mode = DLL off
simsoctb.ram_chip.cmd_task: at time 23397792500.0 ps INFO: ZQ        long = 1
simsoctb.ram_chip.cmd_task: at time 24810597500.0 ps INFO: Activate  bank 0 row 0000
simsoctb.ram_chip.cmd_task: at time 24810612500.0 ps WARNING: tDLLK violation during Read     .
simsoctb.ram_chip.cmd_task: at time 24810612500.0 ps INFO: Read      bank 0 col 000, auto precharge 0
simsoctb.ram_chip.cmd_task: at time 24810632500.0 ps WARNING: tDLLK violation during Read     .
simsoctb.ram_chip.cmd_task: at time 24810632500.0 ps INFO: Read      bank 0 col 008, auto precharge 0
simsoctb.ram_chip.data_task: at time 24810640000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = xxxx
simsoctb.ram_chip.data_task: at time 24810642500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = xxxx
simsoctb.ram_chip.data_task: at time 24810645000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = xxxx
simsoctb.ram_chip.data_task: at time 24810647500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = xxxx
simsoctb.ram_chip.data_task: at time 24810650000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = xxxx
simsoctb.ram_chip.data_task: at time 24810652500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = xxxx
simsoctb.ram_chip.data_task: at time 24810655000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = xxxx
simsoctb.ram_chip.data_task: at time 24810657500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = xxxx
simsoctb.ram_chip.data_task: at time 24810660000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000008 data = xxxx
simsoctb.ram_chip.data_task: at time 24810662500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000009 data = xxxx
simsoctb.ram_chip.data_task: at time 24810665000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000a data = xxxx
simsoctb.ram_chip.data_task: at time 24810667500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000b data = xxxx
simsoctb.ram_chip.data_task: at time 24810670000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000c data = xxxx
simsoctb.ram_chip.data_task: at time 24810672500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000d data = xxxx
simsoctb.ram_chip.data_task: at time 24810675000.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000e data = xxxx
simsoctb.ram_chip.data_task: at time 24810677500.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000f data = xxxx
simsoctb.ram_chip.cmd_task: at time 26031777500.0 ps ERROR: Activate  Failure.  Bank 0 must be Precharged.
jeanthom commented 4 years ago
This issue seems caused by the bank machine FSM. This FSM doesn't ensure that every read/write operation is followed by a precharge command.
jeanthom commented 4 years ago
Fixed by https://github.com/jeanthom/gram/commit/7beb11e5c3183de30b9f781aeda701410d15575c
jeanthom / gram

Fix bank activation failure #32
