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jeanthom / gram

DDR3 controller for nMigen (WIP)
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Wishbone ack doesn't take rddata_valid into account #49

Closed jeanthom closed 4 years ago

jeanthom commented 4 years ago

Just noticed that if I delay the rddata_valid signal, there is no repercution on the wishbone bus... Not sure yet if it's caused by the wishbone frontend or elsewhere.

jeanthom commented 4 years ago

The issue isn't in the wishbone frontend, now taking a look at the crossbar.

jeanthom commented 4 years ago

The issue lies in crossbar: the valid signal isn't correlated at all to what the PHY says, instead it's simply the request signal delayed...