The errata appear to apply also to the MCP2517FD (the errata document for that part is older). No errata are listed for the MCP251863 but since that is an MCP2518FD internally, they can be assumed to be the same.
The specific issues are:
Reads can be corrupted (the drivers already contain counters to detect failed reads in critical registers). The workaround is to enable CRC-protection on SPI reads and then to re-issue corrupted reads.
The maximum SPI SCK frequency should be no more than 17MHz (for a 40MHz chip clock)
Write access to IOCON must be single byte SPI transactions otherwise the two GPIO output values can be erased.
The READ_CRC SPI transaction goes from 6 bytes to 9, with the first two bytes the header, a new length byte, the data bytes, and finally the two CRC bytes. The CRC is transmitted big endian (high byte first, then low byte). The CRC algorithm is a 16-bit CRC with polynomial 0x8005 and an initial value of 0xffff. It is computed over the first three bytes of the header transmitted to the chip, and then the remaining data bytes transmitted from the chip.
There are several silicon bugs around SPI handling that must be worked around. See the errata documentation:
https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/Errata/MCP2518FD-Errata-DS80000789.pdf
The errata appear to apply also to the MCP2517FD (the errata document for that part is older). No errata are listed for the MCP251863 but since that is an MCP2518FD internally, they can be assumed to be the same.
The specific issues are:
The READ_CRC SPI transaction goes from 6 bytes to 9, with the first two bytes the header, a new length byte, the data bytes, and finally the two CRC bytes. The CRC is transmitted big endian (high byte first, then low byte). The CRC algorithm is a 16-bit CRC with polynomial 0x8005 and an initial value of 0xffff. It is computed over the first three bytes of the header transmitted to the chip, and then the remaining data bytes transmitted from the chip.