laforest / FPGADesignElements

A self-contained online book containing a library of FPGA design modules and related coding/design guides.
MIT License
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Possible syntax error at Pipeline_FIFO_Buffer.v #12

Closed rodrigomelo9 closed 3 years ago

rodrigomelo9 commented 3 years ago

Hi @laforest. I was updating my Verifying FOSS HDL-synthesizers project, and there is an error with Pipeline_FIFO_Buffer.v. There are no iverilog or verilator complaints, but Yosys says:

-- Running command `read_verilog -defer examples/Pipeline_FIFO_Buffer.v;' --

1. Executing Verilog-2005 frontend: examples/Pipeline_FIFO_Buffer.v
examples/Pipeline_FIFO_Buffer.v:107: ERROR: syntax error, unexpected ')'

The problem is here (at line 107):

    RAM_Simple_Dual_Port
    #(
        .WORD_WIDTH         (WORD_WIDTH),
        .ADDR_WIDTH         (ADDR_WIDTH),
        .DEPTH              (DEPTH),
        .RAMSTYLE           (RAMSTYLE),
        .READ_NEW_DATA      (0),
        .RW_ADDR_COLLISION  ("no"),
        .USE_INIT_FILE      (0),
        .INIT_FILE          (), // <---- Problem here
        .INIT_VALUE         (WORD_ZERO)
    )
    buffer
    (

I never saw the specification of an empty parameter (yes in signals/ports, where it means no connection). Could you verify if it is legal?

Regards, Rodrigo

laforest commented 3 years ago

Hi @rodrigomelo9,

Thanks for catching that. I checked against Quartus Prime 19.1 and Vivado 2019.2, and both accept a string parameter with a missing string (no string, not an empty string). No warnings, and the module properties show the expected absence of a string.

I dug through the Verilog-2001 (IEEE 1364-2001) standard, and in Appendix A.4.1 (Module instantiation), it explicitly shows that a named parameter assignment is of the form . parameter_identifier ( [ expression ] ), defining the expression as optional.

So it looks like the Yosys parser has a bug. Could you please pass that on to the Yosys maintainers?

Regards, Eric

rodrigomelo9 commented 3 years ago

Hi @laforest

I dug through the Verilog-2001 (IEEE 1364-2001) standard, and in Appendix A.4.1 (Module instantiation), it explicitly shows that a named parameter assignment is of the form . parameter_identifier ( [ expression ] ), defining the expression as optional.

So it looks like the Yosys parser has a bug. Could you please pass that on to the Yosys maintainers?

Of course. Thanks!