Closed rodrigomelo9 closed 3 years ago
Hi @rodrigomelo9,
Thanks for catching that. I checked against Quartus Prime 19.1 and Vivado 2019.2, and both accept a string parameter with a missing string (no string, not an empty string). No warnings, and the module properties show the expected absence of a string.
I dug through the Verilog-2001 (IEEE 1364-2001) standard, and in Appendix A.4.1 (Module instantiation), it explicitly shows that a named parameter assignment is of the form . parameter_identifier ( [ expression ] )
, defining the expression as optional.
So it looks like the Yosys parser has a bug. Could you please pass that on to the Yosys maintainers?
Regards, Eric
Hi @laforest
I dug through the Verilog-2001 (IEEE 1364-2001) standard, and in Appendix A.4.1 (Module instantiation), it explicitly shows that a named parameter assignment is of the form
. parameter_identifier ( [ expression ] )
, defining the expression as optional.So it looks like the Yosys parser has a bug. Could you please pass that on to the Yosys maintainers?
Of course. Thanks!
Hi @laforest. I was updating my Verifying FOSS HDL-synthesizers project, and there is an error with
Pipeline_FIFO_Buffer.v
. There are no iverilog or verilator complaints, but Yosys says:The problem is here (at line 107):
I never saw the specification of an empty parameter (yes in signals/ports, where it means no connection). Could you verify if it is legal?
Regards, Rodrigo