Problems with zero or negative widths

[rodrigomelo9]

Hello @laforest . I have a repo where the idea is to test Yosys against a lot of synthesizable hardware descriptions. I added a directory called FPGADesignElements (in a branch).

The thing is, that I checked your examples with iverilog and the verilator linter, and there are mainly errors related to 0 or negative widths. One example:

* examples/Bitmask_Next_with_Constant_Popcount_ntz.v
examples/Word_Reducer.v:32: error: Concatenation repeat may not be zero in this context.
examples/Logarithm_of_Powers_of_Two.v:103: error: Concatenation repeat may not be zero in this context.
examples/Logarithm_of_Powers_of_Two.v:78: error: Concatenation repeat may not be zero in this context.
examples/Logarithm_of_Powers_of_Two.v:61: error: Concatenation repeat may not be zero in this context.
examples/Adder_Subtractor_Binary.v:31: error: Concatenation repeat may not be zero in this context.
examples/Bit_Shifter.v:82: error: Concatenation repeat may not be zero in this context.
examples/Bit_Shifter.v:83: error: Concatenation repeat may not be zero in this context.
examples/Bitmask_Next_with_Constant_Popcount_ntz.v:64: error: Concatenation repeat may not be zero in this context.
8 error(s) during elaboration.

Without further analysis of each situation, I understand that the problems are related to parameters with the value 0, which seems invalid (so, I think that are not good default values).

In the branch of my repo, there is a Makefile to download the examples and run iverilog and verilator. You can test there. Also, if you want, I can contribute with a Makefile (or bash, let me know what you prefer) for your repository.

[laforest]

Hello Rodrigo. Thanks for including my designs in your test setup. You understand correctly: most parameters are set to 0, or an empty string, in the module definitions. This is intentional, so when a user forgets to set a parameter when instantiating a module, synthesis will (almost always) fail, and linting also. Other default values might not get noticed and cause bugs. This does mean the modules are not synthesizable as defined, but must be either edited to set the parameters, or instantiated separately. I would love to provide an instantiation template for each module, but it's too much manual work to maintain. Would you happen to know of a tool that can generate module instance source from the definition? Regards, Eric

[rodrigomelo9]

I got your point, what bothers me is to have a module which default values are invalid, but I understand that it is a possible option. I n this aspect, I like VHDL were you can specify a range of valid values :P

Anyway, in my case is easy to solve, I can patch the files using sed in my downloaded versions.

I know, but I have not used it yet, symbolator:

Symbolator is a component diagramming tool for VHDL and Verilog. It will parse HDL source files, extract components or modules and render them as an image.

Maybe, it has an option to provide an instantiation template, and if not, it could be implemented using it as base ;-) (the info about parameters and ports is already collected there).

This issue can be closed if, as you said, it is a design decision. Maybe, a notice indicating this situation could be useful (outline section? README.md? both of them?).

Regards

[laforest]

Thanks for the link. I will add a mention of the design intent.

[rodrigomelo9]

I think that Symbolator could be useful for your explanation of each component. It uses Hdlparse under-the-hood to parse Verilog and VHDL, and it can be used to develop what you need (if not already solved, probably, but I don't know where :P).

[laforest]

Oh, that's likley exactly what I need: do the parsing, then I can output the exact format I want. Could be a simple script callable from the text editor. Thanks!

[rodrigomelo9]

Or it could be part of v2h.py. It seems that Hdlparse was not updated for years but maybe is enough here. I need something similar for another project, so I will check.

[mithro]

FYI -- We are using symbolator in the SymbiFlow project for a number of things and might pick up the maintenance + improvements if it is abandoned by its original recreator. We do care more about Verilog rather than VHDL.

[mithro]

Another thought -- if you only want Verilog / SystemVerilog - you might want to checkout SureLog -- it has Python APIs.

You could also potentially use Yosys and just parse the json output. We use that in https://sphinxcontrib-verilog-diagrams.readthedocs.io/en/latest/ and https://github.com/SymbiFlow/python-symbiflow-v2x/pull/36

[laforest]

Thanks all. This issue is closed for now, but I will check those out later. (The website is lagging a little behind the repo right now.)

[laforest]

Update: hdlparse is quite broken for Verilog. Other toolkits are far too heavyweight. (I only need to parse the module header).