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legokor / FPGA-ParallelVideoRx

FPGA parallel video receiver module
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AXI-Stream Video Interface #6

Closed ksstms closed 3 years ago

ksstms commented 3 years ago

Modify the dvp_receiver module's output to be compliant with the AXI4-Stream Video Interface.

This makes it possible to use the receiver with the Xilinx Sensor Demosaic and Video DMA IP cores.

The original dvp_receiver outputs an AXI-Stream packet for a full frame. This means that TLAST is only asserted at the end of the frame.

In the AXI-Stream Video Interface, each row of pixels is a separate packet, thus the TLAST signal is asserted at the end of each row. Frame synchronization is achieved by using an additional TUSER signal as a Start-of-Frame indicator. This is asserted at the first transaction in the frame.

Implementing this is actually simpler than the original module. We need to assert TLAST at the end of each HREF sequence, and TUSER when HREF first goes high after a VSYNC pulse.

ksstms commented 3 years ago

I've added the TUSER signal to the module on the axis_video branch. Also, issue #1 might help with the implementation.