Open sgherbst opened 4 years ago
This has come up in FB's use cases, I think there's also some inconsistency between the SystemVerilog timing model w.r.t. to clocks (this is only for synchronous circuits) and Verilator (e.g. do poke values happen before or after the clock edge).
I'm going to draft a proposal for a new SynchronousTester
that reworks how clock timing semantics are handled. I suspect these changes maybe orthogonal to the discrete simulator time steps, but figured it's worth mentioning. For now I'm going to do it in a separate Tester object so we don't break existing test benches that rely on the current timing semantics.
The meaning of time flow between different kinds of simulation targets has diverged, and even within a given target there are some inconsistencies (e.g., some delays are in seconds, some nanoseconds, and some in time units).
I've reported my observations below on how time is handled in all four transient simulation targets. Lines numbers are with respect to the most recent master branch commit, which is 400b988177fd7091739c9a078f6c76dd10c0e02e. I suggest we give some thought to how to unify and simplify handling of time in these various targets.