Open cai-zhi-jie opened 1 week ago
I have noticed that there is information about the VDD and VSS net in the def file.
But the contest introduction says that "for the sake of simplicity, these circuits do not incorporate power gird or clock tree routing."
Will the benchmark be updated to remove all information about the VDD/VSS net, as in ISPD2024, or should we manually ignore it?
Besides, I also find the clk net in def.
I have noticed that there is information about the VDD and VSS net in the def file.
But the contest introduction says that "for the sake of simplicity, these circuits do not incorporate power gird or clock tree routing."
Will the benchmark be updated to remove all information about the VDD/VSS net, as in ISPD2024, or should we manually ignore it?