de10nano support

[rob-ng15]

I have started trying to modify the de0nano for the de10nano, using the 128mb SDRAM expansion board for MiSTer, the retro console/computer/arcade emulator.

The problem I ma having is that when I use, from the documentation, the correct UART serial_rx (PIN A22) and serial_tx (PIN B21) in platforms/de10nano

("serial", 0,
    Subsignal("tx", Pins("B21"), IOStandard("3.3-V LVTTL")),
    Subsignal("rx", Pins("A22"), IOStandard("3.3-V LVTTL"))
),

I get the following errors: Error (14566): The Fitter cannot place 2 periphery component(s) due to conflicts with existing constraints (2 pin(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (175020): The Fitter cannot place logic pin in region (79, 81) to (79, 81), to which it is constrained, because there are no valid locations in the region for logic of this type. Info (14596): Information about the failing component(s): Info (175028): The pin name(s): serial_rx Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below: Error (184016): There were not enough single-ended input pin locations available (1 location affected) Info (175029): A22 Info (175015): The I/O pad serial_rx is constrained to the location PIN_A22 due to: User Location Constraints (PIN_A22) File: /home/rob/Development/Quartus/Projects/linux-on-litex-vexriscv/build/de10nano/gateware/top.v Line: 6 Info (14709): The constrained I/O pad is contained within this pin Error (175020): The Fitter cannot place logic pin in region (79, 81) to (79, 81), to which it is constrained, because there are no valid locations in the region for logic of this type. Info (14596): Information about the failing component(s): Info (175028): The pin name(s): serial_tx Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below: Error (184016): There were not enough single-ended output pin locations available (1 location affected) Info (175029): B21 Info (175015): The I/O pad serial_tx is constrained to the location PIN_B21 due to: User Location Constraints (PIN_B21) File: /home/rob/Development/Quartus/Projects/linux-on-litex-vexriscv/build/de10nano/gateware/top.v Line: 5 Info (14709): The constrained I/O pad is contained within this pin Error (12289): An error occurred while applying the periphery constraints. Review the offending constraints and rerun the Fitter. Info (11798): Fitter preparation operations ending: elapsed time is 00:00:15 Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error: Quartus Prime Fitter was unsuccessful. 9 errors, 4 warnings Error: Peak virtual memory: 1342 megabytes Error: Processing ended: Wed Nov 27 20:03:50 2019 Error: Elapsed time: 00:00:22 Error: Total CPU time (on all processors): 00:00:22

I can change these pins to general GPIO pins and get a successful compilation. Any ideas?

[enjoy-digital]

Hi @rob-ng15,

sorry for the delay. Can you share the platform file you created so that i do some tests and try to understand? It seems there is a conflict in the constraint file.

[rob-ng15]

Many thanks.

On the DE10nano the UART is connected to the ARM processor (HPS in the FPGA terms) and is not accessible to the FPGA.

I'll dig the file out of my archives, as in the setup that I have it had 128mb sdram, so could be useful.

Some peripherals will need to be via the HPS system.

On Fri, 6 Dec 2019, 15:20 enjoy-digital, notifications@github.com wrote:

Hi @rob-ng15 https://github.com/rob-ng15,

sorry for the delay. Can you share the platform file you created so that i do some tests and try to understand? It seems there is a conflict in the constraint file.

— You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub https://github.com/litex-hub/litex-boards/issues/23?email_source=notifications&email_token=AN4SYTYGOCZTUPJDTLFXJM3QXJUVDA5CNFSM4JSLVMS2YY3PNVWWK3TUL52HS4DFVREXG43VMVBW63LNMVXHJKTDN5WW2ZLOORPWSZGOEGEM5FQ#issuecomment-562613910, or unsubscribe https://github.com/notifications/unsubscribe-auth/AN4SYT5AU776T5AEG6QWAH3QXJUVDANCNFSM4JSLVMSQ .

[rob-ng15]

The PLATFORMS file de10nano.pdf

The TARGETS file de10nano.pdf

These are just modified de0 nano files, with the SDRAM from the MiSTer project linked. These WON'T compile due to the problem with the UART pins, probably due to them being on the ARM processor side.

[AnttiLukats]

you can use jtag_uart that what we do

[enjoy-digital]

@rob-ng15: as @AnttiLukats suggests, you can use the JTAG UART by adding --uart-name=jtag_atlanticwhen building your target file.

[rob-ng15]

Many thanks for the feedback. I believe I have it built for the de10 nano + MiSTer SDRAM and I/O board. Will test when the FTDI lead with pins arrives.

Can I ask where do I put the --uart-name=jtag_atlantic ?

[enjoy-digital]

When building your target, instead if just executing it, do: ./target.py --uart-name=jtag_atlantic

[rob-ng15]

Many thanks for that. I have it running, kind of. I have a system that boots to the BIOS, but due to having to use nios2-terminal to communicate with the board, no way of using lxterm to load and boot the linux image. That may be doable once the breakout cables arrive, fingers cross.

I've attached my files, included are a couple of screenshots. The de10nano is configured for MiSTer, https://github.com/MiSTer-devel/Main_MiSTer/wiki , and has all of the expansion boards, 128MB SDRAM, USB-HUB and I/O board (the USB3 a like port will be used for serial once cables arrive).

To go further with the de10nano, I guess it will be necessary to use the HPS system, to allow USB, ethernet, which is a shame, as it is a great board.

Anyway, for now, here it all is!

de10nanomister.zip

[rob-ng15]

[enjoy-digital]

Nice, thanks for sharing your results! Happy to merge it to litex-boards if you create a pull request for it. (could be located in community). I'm closing this since the problem is now identified and things are working.

[rob-ng15]

Hello.

I've been unable to create a branch/pull request for this code. Can this be done?

[rob-ng15]

I've uploaded my files, so far, to https://github.com/rob-ng15/litex-mister