[chip-test] chip_sw_alert_handler_crashdump

[GregAC]

Test point name

chip_sw_alert_handler_crashdump

Host side component

Unknown

OpenTitanTool infrastructure implemented

None

Silicon Validation (SiVal)

Yes

Emulation Targets

• [ ] None
• [X] CW310
• [x] Hyperdebug + CW310

Contact person

@msfschaffner

Checklist

Please fill out this checklist as items are completed. Link to PRs and issues as appropriate.

• [x] Check if existing test covers most or all of this testpoint (if so, either extend said test to cover all points, or skip the next 3 checkboxes)
• [x] Device-side (C) component developed
• [x] Bazel build rules developed
• [ ] Host-side component developed
• [x] HJSON test plan updated with test name (so it shows up in the dashboard)
• [x] Test added to dvsim nightly regression (and passing at time of checking)
• [x] For SiVal test cases, test is running relevant FPGA or silicon regression

estimate 0.5

[matutem]

This test has some failures due to flash_ctrl. See #20589 .