UVM_ERROR (tl_host_driver.sv:67) [driver] Check failed cfg.a_source_pend_q.size() == * (* [*] vs * [*]) has 1 failures:
Test pwrmgr_lowpower_invalid has 1 failures.
0.pwrmgr_lowpower_invalid.93457763716501404611767655445197294812421893942432372394302448738640560236065\
Line 67, in log /home/gary/Projects/opentitan/scratch/pyproject/pwrmgr-sim-vcs/0.pwrmgr_lowpower_invalid/latest/run.log
Latest report shows 1/50 passing rate, seems to be a geniune regression.
Steps to Reproduce
GitHub Revision: 78ad89d1aa (also reproduced on 6e20c732df3a22edcec054b0f79fd20a99594b76)
dvsim invocation command to reproduce the failure, inclusive of build and run seeds:
util/dvsim/dvsim.py hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson -i pwrmgr_lowpower_invalid --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544 --fixed-seed 93457763716501404611767655445197294812421893942432372394302448738640560236065
Hierarchy of regression failure
Block level
Failure Description
UVM_ERROR (tl_host_driver.sv:67) [driver] Check failed cfg.a_source_pend_q.size() == * (* [*] vs * [*])
has 1 failures:Test pwrmgr_lowpower_invalid has 1 failures.
0.pwrmgr_lowpower_invalid.93457763716501404611767655445197294812421893942432372394302448738640560236065\ Line 67, in log /home/gary/Projects/opentitan/scratch/pyproject/pwrmgr-sim-vcs/0.pwrmgr_lowpower_invalid/latest/run.log
Latest report shows 1/50 passing rate, seems to be a geniune regression.
Steps to Reproduce
util/dvsim/dvsim.py hw/top_earlgrey/ip_autogen/pwrmgr/dv/pwrmgr_sim_cfg.hjson -i pwrmgr_lowpower_invalid --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544 --fixed-seed 93457763716501404611767655445197294812421893942432372394302448738640560236065
Tests with similar or related failures
No response