Technology Mapping of sequential aig fails.

[lesliepy99]

Describe the bug I get an aig of a sequential circuit by abc and yosys, and read in the aig by lorina::read_aiger. However, when I try to run technology mapping and during the step of cut enumeration, I found all the latch nodes have no fanin, and the cut merge step fails.

To Reproduce Steps to reproduce the behavior:

1. Latest(v0.3).

2. A complete snippet of your code (usually a cpp file including main). the same code in the example.

3. The benchmark circuit for which the error occurs: attached (tmp.aig.zip) tmp.aig.zip

4. segment fault.

Environment

• OS: [ubuntu 20.04]
• Compiler: [13.0.0]
• Compilation mode: [RELEASE]

Check list

• [x] I have tried to run in DEBUG mode and there was no assertion failure (or the reported bug is an assertion failure).
• [x] I have made sure that the provided code compiles and the testcase reproduces the error.
• [x] I have minimized the testcase.

[aletempiac]

Hi! The issue has been fixed in #599. Nevertheless, sequential network support in Mockturtle is still limited and under development. Hence, you may encounter other similar issues.

[lesliepy99]

Thanks!