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ludvigsj / dmpro16

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Power saving for Artix-7 #1

Open maltanar opened 8 years ago

maltanar commented 8 years ago

It looks like Xilinx removed the SUSPEND mode from 7-series FPGAs, so there is no explicit sleep mode to be triggered.

Clock gating (stopping the clock while not in operation) is still an option and is discussed in page 57 of the following: http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

So the clock is passed through a BUFGCE (clock buffer) with an enable signal to enable or disable that entire region. Here's a small Verilog example on this: https://forums.xilinx.com/t5/Timing-Analysis/FPGA-clock-gating-implementation/td-p/548555

magnehh commented 8 years ago

I guess we'll just let the FPGA handle the clock stopping/halting internally then.