m-labs / artiq

A leading-edge control system for quantum information experiments
https://m-labs.hk/artiq
GNU Lesser General Public License v3.0
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move ethernet timing constraints of kc705 to MiniSoC #312

Closed enjoy-digital closed 8 years ago

enjoy-digital commented 8 years ago

To be done when we'll figure out a reliable way to apply constraint on signals with Vivado ("dont_touch" signal attribute?)

sbourdeauducq commented 8 years ago

What's the current status on that?

enjoy-digital commented 8 years ago

There are two things:

We could do 2) without 1) but we still have to fix 1) since I'm not sure timings constraints are correcly applied when building with Vivado (the Vivado log should show it when applying the XDC constraints, is there a log somewhere?)

sbourdeauducq commented 8 years ago

http://buildbot.m-labs.hk/builders/artiq-board/builds/134/steps/conda_build/logs/stdio

sbourdeauducq commented 8 years ago

Could this be the reason for the Ethernet bugs we are seeing with some switches?

enjoy-digital commented 8 years ago

Not sure but possible:

WARNING: [Vivado 12-507] No nets matched 'eth_clocks_rx'. [/var/lib/buildbot/slaves/debian-stretch-amd64-2/miniconda/conda-bld/work/misoc_nist_clock_kc705/gateware/top.xdc:1027] CRITICAL WARNING: [Vivado 12-4739] create_clock:No valid object(s) found for '-objects [get_nets eth_clocks_rx]'. [/var/lib/buildbot/slaves/debian-stretch-amd64-2/miniconda/conda-bld/work/misoc_nist_clock_kc705/gateware/top.xdc:1027]

sbourdeauducq commented 8 years ago

Done.