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m-labs / artiq

A leading-edge control system for quantum information experiments
https://m-labs.hk/artiq
GNU Lesser General Public License v3.0
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OSError when trying to build bitstream #392

Closed r-srinivas closed 8 years ago

r-srinivas commented 8 years ago

I'm trying to run this command,

python3.5 -m artiq.gateware.targets.kc705 -H qc1 # or qc2

but get the following error,

Traceback (most recent call last):
  File "/home/rabi/anaconda3/lib/python3.5/runpy.py", line 170, in _run_module_as_main
    "__main__", mod_spec)
  File "/home/rabi/anaconda3/lib/python3.5/runpy.py", line 85, in _run_code
    exec(code, run_globals)
  File "/home/rabi/artiq-dev/artiq/artiq/gateware/targets/kc705.py", line 391, in <module>
    main()
  File "/home/rabi/artiq-dev/artiq/artiq/gateware/targets/kc705.py", line 387, in main
    build_artiq_soc(soc, builder_argdict(args))
  File "/home/rabi/artiq-dev/artiq/artiq/gateware/soc.py", line 61, in build_artiq_soc
    builder.build()
  File "/home/rabi/artiq-dev/misoc/misoc/integration/builder.py", line 156, in build
    run=self.compile_gateware, **kwargs)
  File "/home/rabi/artiq-dev/misoc/misoc/integration/soc_core.py", line 195, in build
    self.platform.build(self, *args, **kwargs)
  File "/home/rabi/artiq-dev/migen/migen/build/xilinx/platform.py", line 28, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/home/rabi/artiq-dev/migen/migen/build/xilinx/ise.py", line 188, in build
    self.map_opt, self.par_opt)
  File "/home/rabi/artiq-dev/migen/migen/build/xilinx/ise.py", line 97, in _run_ise
    settings = common.settings(ise_path, ver, "ISE_DS")
  File "/home/rabi/artiq-dev/migen/migen/build/xilinx/common.py", line 20, in settings
    + path)
OSError: no version directory for Xilinx tools found in /opt/Xilinx

It used to work fine but I'm unable to generate the bitstream. It seems like the /opt/Xilinx folder exists and I've been able to generate bitstreams before. I've updated migen, misoc and artiq. Any idea what could be wrong?

cr1901 commented 8 years ago

This is probably my fault. Yesterday, I committed a patch to unconditionally set the source argument to the Xilinx ISE builder in Migen; building MiSoC bitstreams on Windows was broken without it.

I assume you're using a nix, since Migen is looking for Xilinx in opt/Xilinx; my patch shouldn't have affected the functionality of the nix version of the ISE builder (which would source to True even before last night). I have Xilinx and Linux installed on my netbook. I'll see if I can duplicate/fix later tonight.

r-srinivas commented 8 years ago

I'm not sure if that was it. I tried checking out an older version of migen but that still gave me the same message. I'll try reinstalling my Xilinx stuff.

jordens commented 8 years ago

Try the vivado toolchain Option.

sbourdeauducq commented 8 years ago

@r-srinivas Did you install ISE or Vivado?

r-srinivas commented 8 years ago

Vivado. It was working before for generating the bitstream so I'm not sure what changed. I guess it was maybe when I uninstalled artiq from #361.

sbourdeauducq commented 8 years ago

@r-srinivas ls /opt/Xilinx please.

sbourdeauducq commented 8 years ago

And yes, if you want to build with Vivado, you need to add --toolchain vivado. ISE is the default, and if it is not installed, you get this error message that simply tells you it was not found.

r-srinivas commented 8 years ago 
rabi@68810MAGTRAPVM:/opt$ ls /opt/Xilinx
DocNav  Downloads  Vivado  Vivado_HLS  xic

This was after the reinstall.

If I try --toolchain vivado I get,

Traceback (most recent call last):
  File "/home/rabi/anaconda3/lib/python3.5/runpy.py", line 170, in _run_module_as_main
    "__main__", mod_spec)
  File "/home/rabi/anaconda3/lib/python3.5/runpy.py", line 85, in _run_code
    exec(code, run_globals)
  File "/home/rabi/artiq-dev/artiq/artiq/gateware/targets/kc705.py", line 391, in <module>
    main()
  File "/home/rabi/artiq-dev/artiq/artiq/gateware/targets/kc705.py", line 387, in main
    build_artiq_soc(soc, builder_argdict(args))
  File "/home/rabi/artiq-dev/artiq/artiq/gateware/soc.py", line 61, in build_artiq_soc
    builder.build()
  File "/home/rabi/artiq-dev/misoc/misoc/integration/builder.py", line 156, in build
    run=self.compile_gateware, **kwargs)
  File "/home/rabi/artiq-dev/misoc/misoc/integration/soc_core.py", line 195, in build
    self.platform.build(self, *args, **kwargs)
  File "/home/rabi/artiq-dev/migen/migen/build/xilinx/platform.py", line 28, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/home/rabi/artiq-dev/migen/migen/build/xilinx/vivado.py", line 131, in build
    _run_vivado(build_name, toolchain_path, source)
  File "/home/rabi/artiq-dev/migen/migen/build/xilinx/vivado.py", line 70, in _run_vivado
    raise OSError("Subprocess failed")
OSError: Subprocess failed
sbourdeauducq commented 8 years ago

No error before the Python traceback?

r-srinivas commented 8 years ago 
rabi@68810MAGTRAPVM:~/artiq-dev$ python3.5 -m artiq.gateware.targets.kc705 -H nist_qc2 --toolchain vivado
make: Entering directory `/home/rabi/artiq-dev/misoc_nist_qc2_kc705/software/libcompiler_rt'
 CC       divsi3.o
 CC       modsi3.o
 CC       comparesf2.o
 CC       comparedf2.o
 CC       negsf2.o
 CC       negdf2.o
 CC       addsf3.o
 CC       subsf3.o
 CC       mulsf3.o
 CC       divsf3.o
 CC       lshrdi3.o
 CC       muldi3.o
 CC       divdi3.o
 CC       ashldi3.o
 CC       ashrdi3.o
 CC       udivmoddi4.o
 CC       floatsisf.o
 CC       floatunsisf.o
 CC       fixsfsi.o
 CC       fixdfdi.o
 CC       fixunssfsi.o
 CC       fixunsdfdi.o
 CC       adddf3.o
 CC       subdf3.o
 CC       muldf3.o
 CC       divdf3.o
 CC       floatsidf.o
 CC       floatunsidf.o
 CC       floatdidf.o
 CC       fixdfsi.o
 CC       fixunsdfsi.o
 CC       clzsi2.o
 CC       ctzsi2.o
 CC       udivdi3.o
 CC       umoddi3.o
 CC       moddi3.o
 CC       ucmpdi2.o
 CC       powidf2.o
 AR       libcompiler_rt.a
make: Leaving directory `/home/rabi/artiq-dev/misoc_nist_qc2_kc705/software/libcompiler_rt'
make: Entering directory `/home/rabi/artiq-dev/misoc_nist_qc2_kc705/software/libbase'
 CC       crt0-or1k.o
 CC       exception.o
 CC       libc.o
 CC       errno.o
 CC       crc16.o
 CC       crc32.o
 CC       console.o
 CC       system.o
 CC       id.o
 CC       uart.o
 CC       time.o
 CC       qsort.o
 CC       strtod.o
 CC       spiflash.o
 CC       vsnprintf.o
 AR       libbase.a
 CC       vsnprintf-nofloat.o
 AR       libbase-nofloat.a
make: Leaving directory `/home/rabi/artiq-dev/misoc_nist_qc2_kc705/software/libbase'
make: Entering directory `/home/rabi/artiq-dev/misoc_nist_qc2_kc705/software/libnet'
 CC       microudp.o
 CC       tftp.o
 AR       libnet.a
make: Leaving directory `/home/rabi/artiq-dev/misoc_nist_qc2_kc705/software/libnet'
make: Entering directory `/home/rabi/artiq-dev/misoc_nist_qc2_kc705/software/bios'
 CC       isr.o
 CC       sdram.o
In file included from /home/rabi/artiq-dev/misoc/misoc/software/bios/sdram.c:7:
/home/rabi/artiq-dev/misoc_nist_qc2_kc705/software/include/generated/sdram_phy.h:16:13: warning: 
      unused function 'command_p1' [-Wunused-function]
static void command_p1(int cmd)
            ^
/home/rabi/artiq-dev/misoc_nist_qc2_kc705/software/include/generated/sdram_phy.h:26:13: warning: 
      unused function 'command_p3' [-Wunused-function]
static void command_p3(int cmd)
            ^
2 warnings generated.
 CC       main.o
 CC       boot-helper-or1k.o
 CC       boot.o
 LD       bios.elf
chmod -x bios.elf
 OBJCOPY  bios.bin
chmod -x bios.bin
python3 -m misoc.tools.mkmscimg bios.bin
make: Leaving directory `/home/rabi/artiq-dev/misoc_nist_qc2_kc705/software/bios'
make: Entering directory `/home/rabi/artiq-dev/misoc_nist_qc2_kc705/software/liballoc'
 CC       alloc.o
 AR       liballoc.a
make: Leaving directory `/home/rabi/artiq-dev/misoc_nist_qc2_kc705/software/liballoc'
make: Entering directory `/home/rabi/artiq-dev/misoc_nist_qc2_kc705/software/libm'
 CC       k_standard.o
/home/rabi/artiq-dev/misoc/misoc/software/libm/k_standard.c:107:14: warning: 
      implicit declaration of function 'fputs' is invalid in C99
      [-Wimplicit-function-declaration]
                    (void) WRITE2("acos: DOMAIN error\n", 19);
                           ^
/home/rabi/artiq-dev/misoc/misoc/software/libm/k_standard.c:20:21: note: 
      expanded from macro 'WRITE2'
#define WRITE2(u,v)     fputs(u, stderr)
                        ^
1 warning generated.
 CC       k_rem_pio2.o
 CC       k_cos.o
 CC       k_sin.o
 CC       k_tan.o
/home/rabi/artiq-dev/misoc/misoc/software/libm/k_tan.c:1:9: warning: unknown
      pragma ignored [-Wunknown-pragmas]
#pragma ident "@(#)k_tan.c 1.5 04/04/22 SMI"
        ^
1 warning generated.
 CC       e_acos.o
 CC       e_acosh.o
 CC       e_asin.o
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_asin.c:87:6: warning: variable
      't' is used uninitialized whenever 'if' condition is false
      [-Wsometimes-uninitialized]
                if(huge+x>one) return x;/* return x with inexact if x!=0*/
                   ^~~~~~~~~~
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_asin.c:90:7: note: 
      uninitialized use occurs here
                p = t*(pS0+t*(pS1+t*(pS2+t*(pS3+t*(pS4+t*pS5)))));
                    ^
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_asin.c:87:3: note: remove the
      'if' if its condition is always true
                if(huge+x>one) return x;/* return x with inexact if x!=0*/
                ^~~~~~~~~~~~~~~
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_asin.c:76:10: note: initialize
      the variable 't' to silence this warning
        double t,w,p,q,c,r,s;
                ^
                 = 0.0
1 warning generated.
 CC       e_atan2.o
 CC       e_atanh.o
 CC       e_cosh.o
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_cosh.c:81:24: warning: '&&'
      within '||' [-Wlogical-op-parentheses]
              (ix==0x408633ce)&&(lx<=(unsigned)0x8fb9f87d)) {
              ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_cosh.c:81:24: note: place
      parentheses around the '&&' expression to silence this warning
              (ix==0x408633ce)&&(lx<=(unsigned)0x8fb9f87d)) {
                              ^
              (                                           )
1 warning generated.
 CC       e_exp.o
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_exp.c:140:9: warning: variable
      'k' is used uninitialized whenever 'if' condition is false
      [-Wsometimes-uninitialized]
            if(huge+x>one) return one+x;/* trigger inexact */
               ^~~~~~~~~~
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_exp.c:147:5: note: 
      uninitialized use occurs here
        if(k==0)        return one-((x*c)/(c-2.0)-x); 
           ^
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_exp.c:140:6: note: remove the
      'if' if its condition is always true
            if(huge+x>one) return one+x;/* trigger inexact */
            ^~~~~~~~~~~~~~~
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_exp.c:109:7: note: initialize
      the variable 'k' to silence this warning
        int k,xsb;
             ^
              = 0
1 warning generated.
 CC       e_fmod.o
 CC       e_gamma.o
 CC       e_gamma_r.o
 CC       e_hypot.o
 CC       e_j0.o
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j0.c:338:10: warning: variable
      'p' is used uninitialized whenever 'if' condition is false
      [-Wsometimes-uninitialized]
        else if(ix>=0x40000000){p = pR2; q= pS2;}
                ^~~~~~~~~~~~~~
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j0.c:340:6: note: 
      uninitialized use occurs here
        r = p[0]+z*(p[1]+z*(p[2]+z*(p[3]+z*(p[4]+z*p[5]))));
            ^
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j0.c:338:7: note: remove the
      'if' if its condition is always true
        else if(ix>=0x40000000){p = pR2; q= pS2;}
             ^~~~~~~~~~~~~~~~~~
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j0.c:328:17: note: initialize
      the variable 'p' to silence this warning
        const double *p,*q;
                       ^
                        = 0
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j0.c:338:10: warning: variable
      'q' is used uninitialized whenever 'if' condition is false
      [-Wsometimes-uninitialized]
        else if(ix>=0x40000000){p = pR2; q= pS2;}
                ^~~~~~~~~~~~~~
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j0.c:341:13: note: 
      uninitialized use occurs here
        s = one+z*(q[0]+z*(q[1]+z*(q[2]+z*(q[3]+z*q[4]))));
                   ^
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j0.c:338:7: note: remove the
      'if' if its condition is always true
        else if(ix>=0x40000000){p = pR2; q= pS2;}
             ^~~~~~~~~~~~~~~~~~
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j0.c:328:20: note: initialize
      the variable 'q' to silence this warning
        const double *p,*q;
                          ^
                           = 0
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j0.c:473:10: warning: variable
      'p' is used uninitialized whenever 'if' condition is false
      [-Wsometimes-uninitialized]
        else if(ix>=0x40000000){p = qR2; q= qS2;}
                ^~~~~~~~~~~~~~
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j0.c:475:6: note: 
      uninitialized use occurs here
        r = p[0]+z*(p[1]+z*(p[2]+z*(p[3]+z*(p[4]+z*p[5]))));
            ^
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j0.c:473:7: note: remove the
      'if' if its condition is always true
        else if(ix>=0x40000000){p = qR2; q= qS2;}
             ^~~~~~~~~~~~~~~~~~
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j0.c:463:17: note: initialize
      the variable 'p' to silence this warning
        const double *p,*q;
                       ^
                        = 0
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j0.c:473:10: warning: variable
      'q' is used uninitialized whenever 'if' condition is false
      [-Wsometimes-uninitialized]
        else if(ix>=0x40000000){p = qR2; q= qS2;}
                ^~~~~~~~~~~~~~
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j0.c:476:13: note: 
      uninitialized use occurs here
        s = one+z*(q[0]+z*(q[1]+z*(q[2]+z*(q[3]+z*(q[4]+z*q[5])))));
                   ^
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j0.c:473:7: note: remove the
      'if' if its condition is always true
        else if(ix>=0x40000000){p = qR2; q= qS2;}
             ^~~~~~~~~~~~~~~~~~
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j0.c:463:20: note: initialize
      the variable 'q' to silence this warning
        const double *p,*q;
                          ^
                           = 0
4 warnings generated.
 CC       e_j1.o
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j1.c:336:17: warning: variable
      'p' is used uninitialized whenever 'if' condition is false
      [-Wsometimes-uninitialized]
        else if(ix>=0x40000000){p = pr2; q= ps2;}
                ^~~~~~~~~~~~~~
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j1.c:338:13: note: 
      uninitialized use occurs here
        r = p[0]+z*(p[1]+z*(p[2]+z*(p[3]+z*(p[4]+z*p[5]))));
            ^
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j1.c:336:14: note: remove the
      'if' if its condition is always true
        else if(ix>=0x40000000){p = pr2; q= ps2;}
             ^~~~~~~~~~~~~~~~~~
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j1.c:326:17: note: initialize
      the variable 'p' to silence this warning
        const double *p,*q;
                       ^
                        = 0
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j1.c:336:17: warning: variable
      'q' is used uninitialized whenever 'if' condition is false
      [-Wsometimes-uninitialized]
        else if(ix>=0x40000000){p = pr2; q= ps2;}
                ^~~~~~~~~~~~~~
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j1.c:339:20: note: 
      uninitialized use occurs here
        s = one+z*(q[0]+z*(q[1]+z*(q[2]+z*(q[3]+z*q[4]))));
                   ^
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j1.c:336:14: note: remove the
      'if' if its condition is always true
        else if(ix>=0x40000000){p = pr2; q= ps2;}
             ^~~~~~~~~~~~~~~~~~
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j1.c:326:20: note: initialize
      the variable 'q' to silence this warning
        const double *p,*q;
                          ^
                           = 0
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j1.c:472:10: warning: variable
      'p' is used uninitialized whenever 'if' condition is false
      [-Wsometimes-uninitialized]
        else if(ix>=0x40000000){p = qr2; q= qs2;}
                ^~~~~~~~~~~~~~
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j1.c:474:6: note: 
      uninitialized use occurs here
        r = p[0]+z*(p[1]+z*(p[2]+z*(p[3]+z*(p[4]+z*p[5]))));
            ^
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j1.c:472:7: note: remove the
      'if' if its condition is always true
        else if(ix>=0x40000000){p = qr2; q= qs2;}
             ^~~~~~~~~~~~~~~~~~
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j1.c:462:17: note: initialize
      the variable 'p' to silence this warning
        const double *p,*q;
                       ^
                        = 0
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j1.c:472:10: warning: variable
      'q' is used uninitialized whenever 'if' condition is false
      [-Wsometimes-uninitialized]
        else if(ix>=0x40000000){p = qr2; q= qs2;}
                ^~~~~~~~~~~~~~
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j1.c:475:13: note: 
      uninitialized use occurs here
        s = one+z*(q[0]+z*(q[1]+z*(q[2]+z*(q[3]+z*(q[4]+z*q[5])))));
                   ^
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j1.c:472:7: note: remove the
      'if' if its condition is always true
        else if(ix>=0x40000000){p = qr2; q= qs2;}
             ^~~~~~~~~~~~~~~~~~
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_j1.c:462:20: note: initialize
      the variable 'q' to silence this warning
        const double *p,*q;
                          ^
                           = 0
4 warnings generated.
 CC       e_jn.o
 CC       e_lgamma.o
 CC       e_lgamma_r.o
 CC       e_log.o
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_log.c:115:41: warning: add
      explicit braces to avoid dangling else [-Wdangling-else]
            if(f==zero) if(k==0) return zero;  else {dk=(double)k;
                                               ^
1 warning generated.
 CC       e_log10.o
 CC       e_pow.o
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_pow.c:3:14: warning: unused
      variable 'sccsid' [-Wunused-variable]
static  char sccsid[] = "@(#)e_pow.c 1.5 04/04/22 SMI"; 
             ^
1 warning generated.
 CC       e_rem_pio2.o
 CC       e_remainder.o
 CC       e_scalb.o
 CC       e_sinh.o
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_sinh.c:74:39: warning: '&&'
      within '||' [-Wlogical-op-parentheses]
        if (ix<0x408633CE || (ix==0x408633ce)&&(lx<=(unsigned)0x8fb9f87d)) {
                          ~~ ~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/rabi/artiq-dev/misoc/misoc/software/libm/e_sinh.c:74:39: note: place
      parentheses around the '&&' expression to silence this warning
        if (ix<0x408633CE || (ix==0x408633ce)&&(lx<=(unsigned)0x8fb9f87d)) {
                                             ^
                             (                                           )
1 warning generated.
 CC       e_sqrt.o
 CC       w_acos.o
 CC       w_acosh.o
 CC       w_asin.o
 CC       w_atan2.o
 CC       w_atanh.o
 CC       w_cosh.o
 CC       w_exp.o
/home/rabi/artiq-dev/misoc/misoc/software/libm/w_exp.c:24:1: warning: unused
      variable 'o_threshold' [-Wunused-const-variable]
o_threshold=  7.09782712893383973096e+02,  /* 0x40862E42, 0xFEFA39EF */
^
/home/rabi/artiq-dev/misoc/misoc/software/libm/w_exp.c:25:1: warning: unused
      variable 'u_threshold' [-Wunused-const-variable]
u_threshold= -7.45133219101941108420e+02;  /* 0xc0874910, 0xD52D3051 */
^
2 warnings generated.
 CC       w_fmod.o
 CC       w_gamma.o
 CC       w_gamma_r.o
/home/rabi/artiq-dev/misoc/misoc/software/libm/w_gamma_r.c:22:9: warning: no
      previous prototype for function 'gamma_r' [-Wmissing-prototypes]
        double gamma_r(double x, int *signgamp) /* wrapper lgamma_r */
               ^
1 warning generated.
 CC       w_hypot.o
 CC       w_j0.o
 CC       w_j1.o
 CC       w_jn.o
 CC       w_lgamma.o
 CC       w_lgamma_r.o
/home/rabi/artiq-dev/misoc/misoc/software/libm/w_lgamma_r.c:22:9: warning: no
      previous prototype for function 'lgamma_r' [-Wmissing-prototypes]
        double lgamma_r(double x, int *signgamp) /* wrapper lgamma_r */
               ^
1 warning generated.
 CC       w_log.o
 CC       w_log10.o
 CC       w_pow.o
 CC       w_remainder.o
 CC       w_scalb.o
 CC       w_sinh.o
 CC       w_sqrt.o
 CC       s_asinh.o
 CC       s_atan.o
 CC       s_cbrt.o
 CC       s_ceil.o
 CC       s_copysign.o
 CC       s_cos.o
 CC       s_erf.o
 CC       s_expm1.o
/home/rabi/artiq-dev/misoc/misoc/software/libm/s_expm1.c:196:10: warning: add
      explicit braces to avoid dangling else [-Wdangling-else]
                else          return  one+2.0*(x-e);
                ^
1 warning generated.
 CC       s_fabs.o
 CC       s_finite.o
 CC       s_floor.o
 CC       s_frexp.o
 CC       s_ilogb.o
 CC       s_isnan.o
 CC       s_ldexp.o
 CC       s_lib_version.o
 CC       s_log1p.o
/home/rabi/artiq-dev/misoc/misoc/software/libm/s_log1p.c:155:4: warning: add
      explicit braces to avoid dangling else [-Wdangling-else]
                        else {c += k*ln2_lo; return k*ln2_hi+c;}
                        ^
1 warning generated.
 CC       s_logb.o
 CC       s_matherr.o
 CC       s_modf.o
 CC       s_nextafter.o
 CC       s_rint.o
 CC       s_scalbn.o
/home/rabi/artiq-dev/misoc/misoc/software/libm/s_scalbn.c:59:6: warning: add
      explicit braces to avoid dangling else [-Wdangling-else]
            else return tiny*copysign(tiny,x);  /*underflow*/
            ^
1 warning generated.
 CC       s_signgam.o
 CC       s_significand.o
 CC       s_sin.o
 CC       s_tan.o
 CC       s_tanh.o
 AR       libm.a
make: Leaving directory `/home/rabi/artiq-dev/misoc_nist_qc2_kc705/software/libm'
make: Entering directory `/home/rabi/artiq-dev/misoc_nist_qc2_kc705/software/libdyld'
 CC       dyld.o
 AR       libdyld.a
make: Leaving directory `/home/rabi/artiq-dev/misoc_nist_qc2_kc705/software/libdyld'
make: Entering directory `/home/rabi/artiq-dev/misoc_nist_qc2_kc705/software/libunwind'
 CC       UnwindRegistersSave.o
 CC       UnwindRegistersRestore.o
 CC       UnwindLevel1.o
 CX       libunwind.o
 AR       libunwind.a
make: Leaving directory `/home/rabi/artiq-dev/misoc_nist_qc2_kc705/software/libunwind'
make: Entering directory `/home/rabi/artiq-dev/misoc_nist_qc2_kc705/software/liblwip'
rm -f lwipopts.h
rm -f arch
ln -s /home/rabi/artiq-dev/artiq/artiq/runtime/liblwip/lwipopts.h lwipopts.h
ln -s /home/rabi/artiq-dev/artiq/artiq/runtime/liblwip/arch arch
mkdir -p core/ipv4
mkdir -p netif
mkdir -p netif/ppp
 CC       core/mem.o
 CC       core/memp.o
 CC       core/netif.o
 CC       core/pbuf.o
 CC       core/raw.o
 CC       core/stats.o
 CC       core/sys.o
 CC       core/tcp.o
 CC       core/tcp_in.o
 CC       core/tcp_out.o
 CC       core/udp.o
 CC       core/inet_chksum.o
 CC       core/timers.o
 CC       core/init.o
 CC       core/ipv4/icmp.o
 CC       core/ipv4/ip4.o
 CC       core/ipv4/ip4_addr.o
 CC       core/ipv4/ip_frag.o
 CC       netif/etharp.o
 CC       netif/ppp/auth.o
 CC       netif/ppp/fsm.o
 CC       netif/ppp/ipcp.o
 CC       netif/ppp/lcp.o
 CC       netif/ppp/magic.o
 CC       netif/ppp/ppp.o
 CC       netif/ppp/pppos.o
 CC       netif/ppp/utils.o
 CC       netif/ppp/vj.o
 CC       liteethif.o
 AR       liblwip.a
make: Leaving directory `/home/rabi/artiq-dev/misoc_nist_qc2_kc705/software/liblwip'
make: Entering directory `/home/rabi/artiq-dev/misoc_nist_qc2_kc705/software/runtime'
 CC       isr.o
 CC       clock.o
 CC       rtiocrg.o
 CC       flash_storage.o
 CC       mailbox.o
 CC       session.o
 CC       log.o
 CC       analyzer.o
 CC       moninj.o
 CC       net_server.o
 CC       bridge_ctl.o
 CC       ksupport.o
 CC       artiq_personality.o
 CC       bridge.o
 CC       rtio.o
 CC       dds.o
 CC       i2c.o
 LD       ksupport.elf
 LD       ksupport_data.o
 CC       kloader.o
 CC       test_mode.o
 CC       main.o
 LD       runtime.elf
 OBJCOPY  runtime.bin
 MSCIMG   runtime.fbi
make: Leaving directory `/home/rabi/artiq-dev/misoc_nist_qc2_kc705/software/runtime'

****** Vivado v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source top.tcl
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_cpu_cappuccino.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_cpu_cappuccino.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_cpu_cappuccino.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_fetch_espresso.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_fetch_espresso.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_fetch_espresso.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_icache.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_icache.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_icache.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_i2f.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_i2f.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_i2f.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_dmmu.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_dmmu.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_dmmu.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_dcache.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_dcache.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_dcache.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_ticktimer.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_ticktimer.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_ticktimer.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_addsub.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_addsub.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_addsub.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_rf_cappuccino.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_rf_cappuccino.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_rf_cappuccino.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_simple_dpram_sclk.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_simple_dpram_sclk.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_simple_dpram_sclk.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_pic.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_pic.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_pic.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_fetch_tcm_prontoespresso.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_fetch_tcm_prontoespresso.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_fetch_tcm_prontoespresso.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_muldiv.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_muldiv.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_muldiv.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_true_dpram_sclk.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_true_dpram_sclk.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_true_dpram_sclk.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_execute_ctrl_cappuccino.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_execute_ctrl_cappuccino.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_execute_ctrl_cappuccino.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_rf_espresso.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_rf_espresso.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_rf_espresso.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_lsu_espresso.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_lsu_espresso.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_lsu_espresso.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_bus_if_wb32.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_bus_if_wb32.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_bus_if_wb32.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_wb_mux_cappuccino.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_wb_mux_cappuccino.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_wb_mux_cappuccino.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_cfgrs.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_cfgrs.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_cfgrs.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx-sprs.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx-sprs.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx-sprs.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_cpu.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_cpu.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_cpu.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_branch_prediction.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_branch_prediction.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_branch_prediction.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_lsu_cappuccino.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_lsu_cappuccino.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_lsu_cappuccino.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_ctrl_cappuccino.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_ctrl_cappuccino.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_ctrl_cappuccino.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx-defines.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx-defines.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx-defines.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_ctrl_espresso.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_ctrl_espresso.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_ctrl_espresso.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_immu.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_immu.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_immu.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_cpu_prontoespresso.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_cpu_prontoespresso.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_cpu_prontoespresso.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_top.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_top.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_top.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_fetch_cappuccino.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_fetch_cappuccino.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_fetch_cappuccino.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_bus_if_avalon.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_bus_if_avalon.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_bus_if_avalon.v:]
# add_files {top.v}
# set_property library work [get_files {top.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc_nist_qc2_kc705/gateware/top.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_f2i.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_f2i.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_f2i.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_wb_mux_espresso.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_wb_mux_espresso.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_wb_mux_espresso.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_decode.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_decode.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_decode.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_cache_lru.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_cache_lru.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_cache_lru.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_cmp.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_cmp.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_cmp.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_fetch_prontoespresso.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_fetch_prontoespresso.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_fetch_prontoespresso.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_store_buffer.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_store_buffer.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_store_buffer.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_execute_alu.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_execute_alu.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_execute_alu.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_rnd.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_rnd.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/pfpu32/pfpu32_rnd.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_cpu_espresso.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_cpu_espresso.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_cpu_espresso.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_ctrl_prontoespresso.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_ctrl_prontoespresso.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_ctrl_prontoespresso.v:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_utils.vh}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_utils.vh}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_utils.vh:]
# add_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_decode_execute_cappuccino.v}
# set_property library work [get_files {/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_decode_execute_cappuccino.v}]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [/home/rabi/artiq-dev/misoc/misoc/cores/mor1kx/verilog/rtl/verilog/mor1kx_decode_execute_cappuccino.v:]
# read_xdc top.xdc
# synth_design -top top -part xc7k325t-ffg900-2 -include_dirs {}
Command: synth_design -top top -part xc7k325t-ffg900-2 -include_dirs {}
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7k325t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k325t'
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 1039.438 ; gain = 192.375 ; free physical = 1770 ; free virtual = 7241
---------------------------------------------------------------------------------
ERROR: [Synth 8-439] module 'top' not found
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1078.812 ; gain = 231.750 ; free physical = 1729 ; free virtual = 7200
---------------------------------------------------------------------------------
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
2 Infos, 0 Warnings, 0 Critical Warnings and 2 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Wed Apr 13 10:30:46 2016...
Traceback (most recent call last):
  File "/home/rabi/anaconda3/lib/python3.5/runpy.py", line 170, in _run_module_as_main
    "__main__", mod_spec)
  File "/home/rabi/anaconda3/lib/python3.5/runpy.py", line 85, in _run_code
    exec(code, run_globals)
  File "/home/rabi/artiq-dev/artiq/artiq/gateware/targets/kc705.py", line 391, in <module>
    main()
  File "/home/rabi/artiq-dev/artiq/artiq/gateware/targets/kc705.py", line 387, in main
    build_artiq_soc(soc, builder_argdict(args))
  File "/home/rabi/artiq-dev/artiq/artiq/gateware/soc.py", line 61, in build_artiq_soc
    builder.build()
  File "/home/rabi/artiq-dev/misoc/misoc/integration/builder.py", line 156, in build
    run=self.compile_gateware, **kwargs)
  File "/home/rabi/artiq-dev/misoc/misoc/integration/soc_core.py", line 195, in build
    self.platform.build(self, *args, **kwargs)
  File "/home/rabi/artiq-dev/migen/migen/build/xilinx/platform.py", line 28, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/home/rabi/artiq-dev/migen/migen/build/xilinx/vivado.py", line 131, in build
    _run_vivado(build_name, toolchain_path, source)
  File "/home/rabi/artiq-dev/migen/migen/build/xilinx/vivado.py", line 70, in _run_vivado
    raise OSError("Subprocess failed")
OSError: Subprocess failed

There were some warnings before but nothing stopped it.

sbourdeauducq commented 8 years ago

The relevant error is:

ERROR: [Synth 8-439] module 'top' not found

What does the generated Verilog (misoc_nist_qc1_kc705/gateware/top.v) look like? It should have module top( as second line.

r-srinivas commented 8 years ago 
/* Machine-generated using Migen */
module user_sma_clock_n(
    input serial_cts,
    input serial_rts,
    output reg serial_tx,
    input serial_rx,
    input clk200_p,
    input clk200_n,
    input cpu_reset,
    output [15:0] ddram_a,
    output [2:0] ddram_ba,
    output ddram_ras_n,
    output ddram_cas_n,
    output ddram_we_n,
    output ddram_cs_n,
    output [7:0] ddram_dm,
    inout [63:0] ddram_dq,
    output [7:0] ddram_dqs_p,
    output [7:0] ddram_dqs_n,
    output ddram_clk_p,
    output ddram_clk_n,
    output ddram_cke,
    output ddram_odt,
    output ddram_reset_n,

I can paste the rest of the file if you want but it's a little long.

sbourdeauducq commented 8 years ago

Uhm, there is obviously something wrong with module user_sma_clock_n(. Did you change migen, misoc or artiq in any way, or is this the original code?

r-srinivas commented 8 years ago

I had checked out an earlier version of migen. I tried with the latest version of migen and get this error when trying python3.5 -m artiq.gateware.targets.kc705 -H nist_qc2 --toolchain vivado .

Traceback (most recent call last):
  File "/home/rabi/anaconda3/lib/python3.5/runpy.py", line 170, in _run_module_as_main
    "__main__", mod_spec)
  File "/home/rabi/anaconda3/lib/python3.5/runpy.py", line 85, in _run_code
    exec(code, run_globals)
  File "/home/rabi/artiq-dev/artiq/artiq/gateware/targets/kc705.py", line 411, in <module>
    main()
  File "/home/rabi/artiq-dev/artiq/artiq/gateware/targets/kc705.py", line 407, in main
    build_artiq_soc(soc, builder_argdict(args))
  File "/home/rabi/artiq-dev/artiq/artiq/gateware/soc.py", line 61, in build_artiq_soc
    builder.build()
  File "/home/rabi/artiq-dev/misoc/misoc/integration/builder.py", line 156, in build
    run=self.compile_gateware, **kwargs)
  File "/home/rabi/artiq-dev/misoc/misoc/integration/soc_core.py", line 195, in build
    self.platform.build(self, *args, **kwargs)
  File "/home/rabi/artiq-dev/migen/migen/build/xilinx/platform.py", line 28, in build
    return self.toolchain.build(self, *args, **kwargs)
  File "/home/rabi/artiq-dev/migen/migen/build/xilinx/vivado.py", line 124, in build
    named_sc, named_pc = platform.resolve_signals(v_output.ns)
  File "/home/rabi/artiq-dev/migen/migen/build/generic_platform.py", line 324, in resolve_signals
    sc = self.constraint_manager.get_sig_constraints()
  File "/home/rabi/artiq-dev/migen/migen/build/generic_platform.py", line 215, in get_sig_constraints
    pins = self.connector_manager.resolve_identifiers(pins)
  File "/home/rabi/artiq-dev/migen/migen/build/generic_platform.py", line 128, in resolve_identifiers
    r.append(self.connector_table[conn][pn])
KeyError: 'FMC'
sbourdeauducq commented 8 years ago

Right, @dhslichter did not test his patch. Let me fix it...

sbourdeauducq commented 8 years ago

In the meantime, QC1 and Clock should be unaffected by the KeyError.

sbourdeauducq commented 8 years ago

KeyError with QC2 fixed in 212ee8ca35ec36800898cdb0390868a66c35ba51.

r-srinivas commented 8 years ago

Looks like it worked for nist_qc1, thanks!

INFO: [Vivado 12-3199] DRC finished with 0 Errors, 42 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Bitstream compression saved 63200768 bits.
Writing bitstream ./top.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.).
INFO: [Common 17-186] '/home/rabi/artiq-dev/artiq/misoc_nist_qc1_kc705/gateware/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Wed Apr 13 11:12:48 2016. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2015.4/doc/webtalk_introduction.html.
INFO: [Common 17-83] Releasing license: Implementation
write_bitstream: Time (s): cpu = 00:01:30 ; elapsed = 00:01:29 . Memory (MB): peak = 2707.996 ; gain = 324.340 ; free physical = 164 ; free virtual = 5685
# write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 top.bit" -file top.bin
Creating config memory files...
Creating bitstream load up from address 0x00000000
Loading bitfile top.bit
Writing file ./top.bin
Writing log file ./top.prm
===================================
Configuration Memory information
===================================
File Format        BIN
Interface          SPIX4
Size               16M
Start Address      0x00000000
End Address        0x00FFFFFF

Addr1         Addr2         Date                    File(s)
0x00000000    0x003611D7    Apr 13 11:12:46 2016    top.bit
# quit
INFO: [Common 17-206] Exiting Vivado at Wed Apr 13 11:12:51 2016...
rabi@68810MAGTRAPVM:~/artiq-dev/artiq$

I'll try for qc2 now.

Just for the manual,

Could

For KC705:

$ python3.5 -m artiq.gateware.targets.kc705 -H qc1 # or qc2

be changed to nist_qc1 or nist_qc2?

And in the

Preparing the core device FPGA board

section, could the --toolchain vivado option be added in the instructions? Thanks!

sbourdeauducq commented 8 years ago

Done.