UVM_express

[mahadevaswamy05]

Here we have the UVM examples of the UVM_Express code

http://agilesoc.com/2012/02/24/why-i-like-uvm-express/ http://agilesoc.com/2012/02/20/by-example-test-driven-development-of-verification-ip/ http://agilesoc.com/2012/03/09/uvm-express-step-2-svunit-with-covergroups-and-uvm-agents/ http://agilesoc.com/2012/09/05/youre-either-with-me-or-youre-with-the-uvm-sequencer/ http://agilesoc.com/2012/12/10/uvm-express-so-close-yet/

Course on UVM-Express: https://verificationacademy.com/courses/uvm-express

• [x] #90
• [x] #91
• [x] #92
• [ ] #93
• [ ] #94

[mahadevaswamy05]

Example for UVM_Express code

1. Here they developed the code by using a class, like a UUT file. In this above example we have the below files. -apb_xaction.sv, -apb_if.sv, -apb_mon.sv, -apb_coverage_agent.sv, -apb_coverage.sv

- Click the below details to extend each file.

apb_xaction

**- The below code is the for the apb_xaction code this class name extends from the uvm_sequence_item example class apb_xaction extends uvm_sequence_item;** ```systemverilog `ifndef __APB_XACTION_SV__ `define __APB_XACTION_SV__ `include "uvm_macros.svh" import uvm_pkg::*; class apb_xaction extends uvm_sequence_item; static const logic READ = 0; static const logic WRITE = 1; rand logic kind; rand logic [31:0] addr; rand logic [31:0] data; `uvm_object_utils_begin(apb_xaction) `uvm_field_int(kind, UVM_ALL_ON) `uvm_field_int(addr, UVM_ALL_ON) `uvm_field_int(data, UVM_ALL_ON) `uvm_object_utils_end function new(string name = "apb_xaction"); super.new(name); endfunction endclass `endif ```

apb_if.sv

**The below code is for apb_if.sv Here code is done by using the interface.** ```systemverilog `ifndef __APB_IF__ `define __APB_IF__ interface apb_if #(addrWidth = 8, dataWidth = 32) (input clk); logic [addrWidth-1:0] paddr; logic pwrite; logic psel; logic penable; logic [dataWidth-1:0] pwdata; logic [dataWidth-1:0] prdata; modport mstr ( import async_reset, sync_reset, write, read, input clk, output paddr, output pwrite, output psel, output penable, output pwdata, input prdata ); modport passive_slv ( import capture, input clk, input paddr, input pwrite, input psel, input penable, input pwdata, input prdata ); modport slv ( input clk, input paddr, input pwrite, input psel, input penable, input pwdata, output prdata ); logic write_f; event write_done_e; logic [addrWidth-1:0] next_paddr; logic [dataWidth-1:0] next_pwdata; task write(logic [addrWidth-1:0] addr, logic [dataWidth-1:0] data); write_f = 1; next_paddr = addr; next_pwdata = data; @(write_done_e); endtask logic read_f; event read_done_e; logic [dataWidth-1:0] next_prdata; task read(logic [addrWidth-1:0] addr, output logic [dataWidth-1:0] data); read_f = 1; next_paddr = addr; @(read_done_e); data = next_prdata; endtask logic [2:0] st; const integer IDLE = 0; const integer SETUP = 1; const integer WENABLE = 2; const integer RENABLE = 3; always @(negedge clk) begin case (st) IDLE : begin if (write_f || read_f) begin psel = 1; penable = 0; paddr = next_paddr; pwrite = write_f; if (write_f) begin pwdata = next_pwdata; end st = SETUP; end end SETUP : begin psel = 1; penable = 1; if (write_f) st = WENABLE; else st = RENABLE; end WENABLE : begin -> write_done_e; write_f = 0; // allow a context switch here for back-to-back writes #0; if (write_f) begin psel = 1; penable = 0; paddr = next_paddr; pwdata = next_pwdata; st = SETUP; end else begin psel = 0; penable = 0; paddr = 'hx; pwdata = 'hx; pwrite = 'hx; st = IDLE; end end RENABLE : begin next_prdata = prdata; read_f = 0; -> read_done_e; // allow a context switch here for back-to-back reads #0; if (read_f) begin psel = 1; penable = 0; paddr = next_paddr; st = SETUP; end else begin psel = 0; penable = 0; paddr = 'hx; pwrite = 'hx; st = IDLE; end end endcase end function void async_reset(); write_f = 0; read_f = 0; st = IDLE; paddr = 0; pwrite = 0; psel = 0; penable = 0; pwdata = 0; endfunction task sync_reset(); write_f = 0; read_f = 0; st = IDLE; @(negedge clk); paddr <= 0; pwrite <= 0; psel <= 0; penable <= 0; task capture(output logic write, logic [addrWidth-1:0] addr, logic [dataWidth-1:0] data); @(posedge clk) while (~(psel && penable)) @(posedge clk); write = pwrite; addr = paddr; if (write) data = pwdata; else data = prdata; endtask endinterface `endif ```

apb_mon

_**The below code is for apb_mon.sv this file class name extends from the uvm_monitor. example class apb_mon extends uvm_component;** ```systemverilog `ifndef __APB_MON_SV__ `define __APB_MON_SV__ import uvm_pkg::*; `include "apb_xaction.sv" class apb_mon #(addrWidth = 8, dataWidth = 32) extends uvm_component; `uvm_component_utils(apb_mon) uvm_analysis_port #(apb_xaction) ap; virtual apb_if.passive_slv bfm; // xaction out local apb_xaction tr; // function args from the bfm local logic pwrite; local logic [addrWidth-1:0] paddr; local logic [dataWidth-1:0] pdata; function new(string name = "", uvm_component parent = null); super.new(name, parent); ap = new("ap", this); endfunction function void build_phase(uvm_phase phase); endfunction task main_phase(uvm_phase phase); forever begin tr = apb_xaction::type_id::create("tr"); //--------------------------------- // wait for a xaction from the bfm //--------------------------------- bfm.capture(tr.kind, tr.addr, tr.data); //--------------------------- // put the xaction to the ap //--------------------------- ap.write(tr); end endtask endclass `endif ```

apb_coverage_agent.sv

-**The below code is the apb_coverage_agent.sv here this file class name is extended from the uvm_agent example class class apb_coverage_agent extends uvm_agent;** ```systemverilog `ifndef __APB_COVERAGE_AGENT_SV__ `define __APB_COVERAGE_AGENT_SV__ `include "uvm_macros.svh" `include "apb_mon.sv" `include "apb_coverage.sv" import uvm_pkg::*; class apb_coverage_agent extends uvm_agent; `uvm_component_utils(apb_coverage_agent) virtual apb_if.passive_slv bfm; apb_mon monitor; apb_coverage coverage; function new(string name = "apb_coverage_agent", uvm_component parent = null); super.new(name, parent); endfunction function void build_phase(uvm_phase phase); if( !uvm_config_db#(virtual apb_if.passive_slv)::get( this, "", "bfm", bfm)) begin `uvm_fatal("ENV", "BFM not set") end monitor = apb_mon#(8,32)::type_id::create({ get_name() , "::monitor" }, this); coverage = apb_coverage::type_id::create({ get_name() , "::coverage" }, this); endfunction function void connect_phase(uvm_phase phase); monitor.bfm = bfm; monitor.ap.connect(coverage.analysis_export); endfunction endclass `endif ```

apb_coverage


[mahadevaswamy05]

Show the output - test cases