Closed g-lesssard closed 3 years ago
Let me know if you have time or plan to make the changes in the near future or have moved on to another project :smile:
Hi!
I will have a look shortly!
@g-lesssard, If I fix the things that you mentioned, does verilator compile the rest?
Been a decade since I designed ASICs for a living, but last I checked, open source hdl compilers were not that great. I no longer have access to commercial compilers, but they did not have any issues with the generated code last I checked.
https://github.com/MikePopoloski/slang has no problem parsing the code
Hmm I see... Verilator is a bit over-the-top over certain warnings and such, maybe slang is a bit more permissive regarding these specific things. Verilator is not the best but it's getting a lot of active support from the community so it should be getting better over time. With these small fixes, everything compiles fine with it though!
@g-lesssard See if you have any success with 1.0.11 !
Thanks for the changes! I tried installing it with pip and got this error:
Collecting ipxact2systemverilog
Downloading ipxact2systemverilog-1.0.11.tar.gz (44 kB)
|████████████████████████████████| 44 kB 1.2 MB/s
ERROR: Command errored out with exit status 1:
command: /usr/bin/python3 -c 'import sys, setuptools, tokenize; sys.argv[0] = '"'"'/tmp/pip-install-61kx508t/ipxact2systemverilog/setup.py'"'"'; __file__='"'"'/tmp/pip-install-61kx508t/ipxact2systemverilog/setup.py'"'"';f=getattr(tokenize, '"'"'open'"'"', open)(__file__);code=f.read().replace('"'"'\r\n'"'"', '"'"'\n'"'"');f.close();exec(compile(code, __file__, '"'"'exec'"'"'))' egg_info --egg-base /tmp/pip-install-61kx508t/ipxact2systemverilog/pip-egg-info
cwd: /tmp/pip-install-61kx508t/ipxact2systemverilog/
Complete output (5 lines):
Traceback (most recent call last):
File "<string>", line 1, in <module>
File "/tmp/pip-install-61kx508t/ipxact2systemverilog/setup.py", line 9, in <module>
with open('requirements.txt') as f:
FileNotFoundError: [Errno 2] No such file or directory: 'requirements.txt'
----------------------------------------
ERROR: Command errored out with exit status 1: python setup.py egg_info Check the logs for full command output.
Seems the requirements.txt file is missing...
@g-lesssard unfortunate. Try it again
I assume it is working. Closing
Hi @oddball ,
I am currently in the process of integrating this generator in a Systemverilog project. We plan on using cocotb alongside verilator to make our test benches and test our code. While trying your tool, I had some issues compiling the generated systemverilog code. If we look at the generated example from this repo, the compiler throws these errors.
The fix is simply to add an apostrophe before the first bracket of the array assignments, like this:
source: https://verificationguide.com/systemverilog/systemverilog-fixedsize-array/ (see array assignment section)
This change needs to be made for the
example_regNames
andexample_regUnResetedAddresses
arrays as well.In the
example_regUnResetedAddresses
array, you have an array ofreg
type where you set values like 1 and 0. You need to specify the bit width to insure proper allignment. By default, the compiler doesn't know if the value is on 1 bit, 8, 16, etc...The fix would be this:
The 1'bX tells the compiler that is set on one bit.
The same thing goes for reg7. The issue is that both of these arrays are not the same width of the other registers. All other registers have a width of 32 bits. For example, reg2 is 6 bits, you therefore need to supply where those 6 bits are.
The fix would be something along the lines of this:
The
$bits()
function is something similar to asizeof
in c/c++. This should also be done on thewrite_registers
function on the data part, since it is supplied as 32 bit wide parameter.