Closed siavashr closed 5 years ago
Hi Siavashr, Unfortunately, we are unable to support every development environment. To my knowledge, this project has not been build with Xilinx Vivado.
Thanks for your prompt response. Is there any information about the hierarchy of the RTL design? It can help me to build the design using Xilinx Vivado.
Hey @siavashr if you get this working for Vivado I (and others) would love to see a fork or pull request for this. I suspect being able to build Zipline for FPGAs will be very popular.....
Hi Siavashr,
The entire pipeline, RTL and specifications, are now posted to the respository. Please have a look to determine if this provides the clarity you are looking for.
Best Regards
Hi, I found this project very interesting. I wanted to run it on a Zynq board. I tried to make this project in Xilinx Vivado, however, it seems it's not that straight forward. Can you please give me some information about the way that I make the Vivado project?